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Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x
From: |
Mark Cave-Ayland |
Subject: |
Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x |
Date: |
Fri, 10 May 2019 16:11:53 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 07/05/2019 01:48, Anton Blanchard wrote:
> During the conversion these instructions were incorrectly treated as
> stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
>
> Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}()
> helpers for VSR register access")
> Signed-off-by: Anton Blanchard <address@hidden>
> ---
> target/ppc/translate/vsx-impl.inc.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.inc.c
> b/target/ppc/translate/vsx-impl.inc.c
> index 05b75105be..c13f84e745 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx)
> }
> xth = tcg_temp_new_i64();
> xtl = tcg_temp_new_i64();
> - get_cpu_vsrh(xth, xT(ctx->opcode));
> - get_cpu_vsrl(xtl, xT(ctx->opcode));
> +
> gen_set_access_type(ctx, ACCESS_INT);
> EA = tcg_temp_new();
>
> @@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx)
> tcg_gen_addi_tl(EA, EA, 8);
> tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
> }
> + set_cpu_vsrh(xT(ctx->opcode), xth);
> + set_cpu_vsrl(xT(ctx->opcode), xtl);
> tcg_temp_free(EA);
> tcg_temp_free_i64(xth);
> tcg_temp_free_i64(xtl);
> @@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx)
> }
> xth = tcg_temp_new_i64();
> xtl = tcg_temp_new_i64();
> - get_cpu_vsrh(xth, xT(ctx->opcode));
> - get_cpu_vsrl(xtl, xT(ctx->opcode));
> gen_set_access_type(ctx, ACCESS_INT);
>
> EA = tcg_temp_new();
> @@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx)
> if (ctx->le_mode) {
> gen_bswap16x8(xth, xtl, xth, xtl);
> }
> + set_cpu_vsrh(xT(ctx->opcode), xth);
> + set_cpu_vsrl(xT(ctx->opcode), xtl);
> tcg_temp_free(EA);
> tcg_temp_free_i64(xth);
> tcg_temp_free_i64(xtl);
> @@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx)
> }
> xth = tcg_temp_new_i64();
> xtl = tcg_temp_new_i64();
> - get_cpu_vsrh(xth, xT(ctx->opcode));
> - get_cpu_vsrl(xtl, xT(ctx->opcode));
> gen_set_access_type(ctx, ACCESS_INT);
> EA = tcg_temp_new();
> gen_addr_reg_index(ctx, EA);
> tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
> tcg_gen_addi_tl(EA, EA, 8);
> tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
> + set_cpu_vsrh(xT(ctx->opcode), xth);
> + set_cpu_vsrl(xT(ctx->opcode), xtl);
> tcg_temp_free(EA);
> tcg_temp_free_i64(xth);
> tcg_temp_free_i64(xtl);
I've now had a bit of time to look through this and I believe it is correct, so:
Reviewed-by: Mark Cave-Ayland <address@hidden>
ATB,
Mark.
- Re: [Qemu-devel] [PATCH v2] target/ppc: Fix xxspltib, (continued)
Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x,
Mark Cave-Ayland <=
- Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Anton Blanchard, 2019/05/21
- Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, David Gibson, 2019/05/21
- Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Mark Cave-Ayland, 2019/05/22
- Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, David Gibson, 2019/05/22
- Re: [Qemu-devel] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Mark Cave-Ayland, 2019/05/24
Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/9] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x, Greg Kurz, 2019/05/22
[Qemu-devel] [PATCH 7/9] target/ppc: Fix vrlwmi and vrlwnm, Anton Blanchard, 2019/05/06
[Qemu-devel] [PATCH 8/9] target/ppc: Fix dtstsfi and dtstsfiq, Anton Blanchard, 2019/05/06
[Qemu-devel] [PATCH 9/9] target/ppc: Fix vsum2sws, Anton Blanchard, 2019/05/06