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Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53
From: |
Mark Cave-Ayland |
Subject: |
Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810 |
Date: |
Sun, 5 May 2019 11:41:20 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 04/05/2019 22:02, Artyom Tarasenko wrote:
> AIX/PReP does access to the aliased IO registers of 53810.
> Implement aliasing to make the AIX driver work.
>
> Signed-off-by: Artyom Tarasenko <address@hidden>
> ---
> hw/scsi/lsi53c895a.c | 17 ++++++++++++++---
> 1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
> index da7239d..6b95699 100644
> --- a/hw/scsi/lsi53c895a.c
> +++ b/hw/scsi/lsi53c895a.c
> @@ -2271,6 +2271,9 @@ static void lsi_scsi_realize(PCIDevice *dev, Error
> **errp)
> LSIState *s = LSI53C895A(dev);
> DeviceState *d = DEVICE(dev);
> uint8_t *pci_conf;
> + uint64_t mmio_size;
> + MemoryRegion *mr;
> + uint16_t type = PCI_DEVICE_GET_CLASS(dev)->device_id;
>
> pci_conf = dev->config;
>
> @@ -2279,13 +2282,21 @@ static void lsi_scsi_realize(PCIDevice *dev, Error
> **errp)
> /* Interrupt pin A */
> pci_conf[PCI_INTERRUPT_PIN] = 0x01;
>
> - memory_region_init_io(&s->mmio_io, OBJECT(s), &lsi_mmio_ops, s,
> - "lsi-mmio", 0x400);
> memory_region_init_io(&s->ram_io, OBJECT(s), &lsi_ram_ops, s,
> "lsi-ram", 0x2000);
> memory_region_init_io(&s->io_io, OBJECT(s), &lsi_io_ops, s,
> "lsi-io", 256);
> -
> + if (type == PCI_DEVICE_ID_LSI_53C895A) {
> + mmio_size = 0x400;
> + } else {
> + mr = g_new(MemoryRegion, 1);
In general these days it's worth keeping the reference to the MemoryRegion
within
LSIState since then its lifecycle is more clearly defined.
> + memory_region_init_alias(mr, OBJECT(d), "lsi-io-alias", &s->io_io,
> + 0, 0x80);
> + memory_region_add_subregion_overlap(&s->io_io, 0x80, mr, -1);
> + mmio_size = 0x80;
This feels a little strange - is it possible to see from the datasheets that the
53C895A has 0x400 bytes MMIO whilst the 53C810 has 0x80 bytes MMIO? It's not
clear to
me where the aliasing is happening.
> + }
> + memory_region_init_io(&s->mmio_io, OBJECT(s), &lsi_mmio_ops, s,
> + "lsi-mmio", mmio_size);
> address_space_init(&s->pci_io_as, pci_address_space_io(dev),
> "lsi-pci-io");
> qdev_init_gpio_out(d, &s->ext_irq, 1);
>
>
ATB,
Mark.
- [Qemu-devel] [PATCH v2 0/3] Improve 40p, make AIX 5.1 boot, Artyom Tarasenko, 2019/05/04
- [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Artyom Tarasenko, 2019/05/04
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810,
Mark Cave-Ayland <=
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Artyom Tarasenko, 2019/05/06
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Mark Cave-Ayland, 2019/05/06
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Artyom Tarasenko, 2019/05/07
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Mark Cave-Ayland, 2019/05/17
- Re: [Qemu-devel] [PATCH v2 1/3] lsi53c895a: hide 53c895a registers in 53c810, Paolo Bonzini, 2019/05/20
[Qemu-devel] [PATCH 2/3] 40p and prep: implement PCI bus mastering, Artyom Tarasenko, 2019/05/04
[Qemu-devel] [PATCH v2 3/3] hw/isa/i82378.c: use 1900 as a base year, Artyom Tarasenko, 2019/05/04