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[Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl |
Date: |
Fri, 3 May 2019 22:52:56 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 68 +++++++++++++++---------------------------
1 file changed, 24 insertions(+), 44 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8d08625c33..b5217f632f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5075,40 +5075,26 @@ static void gen_ecowx(DisasContext *ctx)
/* abs - abs. */
static void gen_abs(DisasContext *ctx)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
- tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- gen_set_label(l2);
+ TCGv d = cpu_gpr[rD(ctx->opcode)];
+ TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+ tcg_gen_abs_tl(d, a);
if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ gen_set_Rc0(ctx, d);
}
}
/* abso - abso. */
static void gen_abso(DisasContext *ctx)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- /* Start with XER OV disabled, the most likely case */
- tcg_gen_movi_tl(cpu_ov, 0);
- tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
- tcg_gen_movi_tl(cpu_ov, 1);
- tcg_gen_movi_tl(cpu_so, 1);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- gen_set_label(l3);
+ TCGv d = cpu_gpr[rD(ctx->opcode)];
+ TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
+ tcg_gen_abs_tl(d, a);
+ tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ gen_set_Rc0(ctx, d);
}
}
@@ -5344,34 +5330,28 @@ static void gen_mulo(DisasContext *ctx)
/* nabs - nabs. */
static void gen_nabs(DisasContext *ctx)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- gen_set_label(l2);
+ TCGv d = cpu_gpr[rD(ctx->opcode)];
+ TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+ tcg_gen_abs_tl(d, a);
+ tcg_gen_neg_tl(d, d);
if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ gen_set_Rc0(ctx, d);
}
}
/* nabso - nabso. */
static void gen_nabso(DisasContext *ctx)
{
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- gen_set_label(l2);
+ TCGv d = cpu_gpr[rD(ctx->opcode)];
+ TCGv a = cpu_gpr[rA(ctx->opcode)];
+
+ tcg_gen_abs_tl(d, a);
+ tcg_gen_neg_tl(d, d);
/* nabs never overflows */
tcg_gen_movi_tl(cpu_ov, 0);
if (unlikely(Rc(ctx->opcode) != 0)) {
- gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
+ gen_set_Rc0(ctx, d);
}
}
--
2.17.1
- [Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes, (continued)
- [Qemu-devel] [PATCH v3 19/31] tcg/i386: Support vector scalar shift opcodes, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 18/31] tcg: Add gvec expanders for vector shift by scalar, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 20/31] tcg: Add support for integer absolute value, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 21/31] tcg: Add support for vector absolute value, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 22/31] tcg/i386: Support vector absolute value, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 23/31] tcg/aarch64: Support vector absolute value, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 25/31] target/cris: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 26/31] target/ppc: Use tcg_gen_abs_i32, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 27/31] target/ppc: Use tcg_gen_abs_tl,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 28/31] target/s390x: Use tcg_gen_abs_i64, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 31/31] tcg/aarch64: Do not advertise minmax for MO_64, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 30/31] target/xtensa: Use tcg_gen_abs_i32, Richard Henderson, 2019/05/04
- [Qemu-devel] [PATCH v3 29/31] target/tricore: Use tcg_gen_abs_tl, Richard Henderson, 2019/05/04