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Re: [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::t
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::tlb_fill |
Date: |
Tue, 30 Apr 2019 12:04:46 +0100 |
On Wed, 3 Apr 2019 at 04:52, Richard Henderson
<address@hidden> wrote:
>
> Cc: Edgar E. Iglesias <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> -#if defined(CONFIG_USER_ONLY)
> +bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> + MMUAccessType access_type, int mmu_idx,
> + bool probe, uintptr_t retaddr)
> +{
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> + CPUMBState *env = &cpu->env;
> +
> +#ifndef CONFIG_USER_ONLY
> + uint32_t vaddr, paddr;
> + struct microblaze_mmu_lookup lu;
> + unsigned int hit;
> + int prot;
> +
> + if (mmu_idx == MMU_NOMMU_IDX) {
> + /* MMU disabled or not available. */
> + address &= TARGET_PAGE_MASK;
> + prot = PAGE_BITS;
> + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> + return true;
> + }
> +
> + hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx);
> + if (likely(hit)) {
> + vaddr = address & TARGET_PAGE_MASK;
> + paddr = lu.paddr + vaddr - lu.vaddr;
> +
> + qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
> + mmu_idx, vaddr, paddr, lu.prot);
> + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
> + return true;
> + }
> +
> + /* TLB miss. */
> + if (probe) {
> + return false;
> + }
> +
> + qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
> + mmu_idx, address);
> +
> + switch (lu.err) {
> + case ERR_PROT:
> + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16;
> + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10;
> + break;
> + case ERR_MISS:
> + env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18;
> + env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10;
> + break;
> + default:
> + g_assert_not_reached();
> + }
> +
> + if (cs->exception_index == EXCP_MMU) {
> + cpu_abort(cs, "recursive faults\n");
> + }
> +#endif
> +
> + env->sregs[SR_EAR] = address;
> + cs->exception_index = EXCP_MMU;
> + cpu_loop_exit_restore(cs, retaddr);
> +}
> -int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
> - int mmu_idx)
> -{
> - cs->exception_index = 0xaa;
> - cpu_dump_state(cs, stderr, fprintf, 0);
> - return 1;
> -}
> -
> -#else /* !CONFIG_USER_ONLY */
For the user-mode case we used to set cs->exception_state to 0xaa,
but now we set it to EXCP_MMU. We also set SR_EAR which we didn't
previously.
Otherwise the refactoring looks ok.
thanks
-- PMM
- Re: [Qemu-devel] [PATCH 03/26] target/alpha: Convert to CPUClass::tlb_fill, (continued)
- [Qemu-devel] [PATCH 04/26] target/arm: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 05/26] target/cris: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 06/26] target/hppa: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 08/26] target/lm32: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 07/26] target/i386: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 09/26] target/m68k: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- Re: [Qemu-devel] [PATCH 10/26] target/microblaze: Convert to CPUClass::tlb_fill,
Peter Maydell <=
- [Qemu-devel] [PATCH 11/26] target/mips: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 12/26] target/moxie: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 13/26] target/nios2: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 14/26] target/openrisc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02
- [Qemu-devel] [PATCH 15/26] target/ppc: Convert to CPUClass::tlb_fill, Richard Henderson, 2019/04/02