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[Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profil
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers |
Date: |
Mon, 29 Apr 2019 17:59:53 +0100 |
For M-profile the MVFR* ID registers are memory mapped, in the
range we implement via the NVIC. Allow them to be read.
(If the CPU has no FPU, these registers are defined to be RAZ.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index ab822f42514..45d72f86bdf 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1222,6 +1222,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t
offset, MemTxAttrs attrs)
return 0;
}
return cpu->env.v7m.sfar;
+ case 0xf40: /* MVFR0 */
+ return cpu->isar.mvfr0;
+ case 0xf44: /* MVFR1 */
+ return cpu->isar.mvfr1;
+ case 0xf48: /* MVFR2 */
+ return cpu->isar.mvfr2;
default:
bad_offset:
qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
--
2.20.1
- [Qemu-devel] [PULL 00/42] target-arm queue, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 02/42] hw/ssi/xilinx_spips: Avoid variable length array, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 06/42] target/arm: Implement dummy versions of M-profile FP-related registers, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 05/42] hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers,
Peter Maydell <=
- [Qemu-devel] [PULL 03/42] configure: Remove --source-path option, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 01/42] hw/arm/smmuv3: Remove SMMUNotifierNode, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 07/42] target/arm: Disable most VFP sysregs for M-profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 15/42] target/arm: Clear CONTROL.SFPA in BXNS and BLXNS, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 17/42] target/arm: Allow for floating point in callee stack integrity check, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 13/42] target/arm: Handle floating point registers in exception entry, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 09/42] target/arm: Decode FP instructions for M profile, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 21/42] target/arm: Set FPCCR.S when executing M-profile floating point insns, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 08/42] target/arm: Honour M-profile FP enable bits, Peter Maydell, 2019/04/29
- [Qemu-devel] [PULL 22/42] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set, Peter Maydell, 2019/04/29