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Re: [Qemu-devel] [PATCH 20/26] target/arm: New helper function arm_v7m_m
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 20/26] target/arm: New helper function arm_v7m_mmu_idx_all() |
Date: |
Tue, 23 Apr 2019 17:12:17 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 |
On 4/16/19 5:57 AM, Peter Maydell wrote:
> Add a new helper function which returns the MMU index to use
> for v7M, where the caller specifies all of the security
> state, privilege level and whether the execution priority
> is negative, and reimplement the existing
> arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.
>
> We are going to need this for the lazy-FP-stacking code.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> Suggestions for better function name welcome.
> arm_v7m_mmu_idx_for_secstate_and_priv_and_negpri()
> just seems way too long and unwieldy...
Seems fine.
> ---
> target/arm/cpu.h | 7 +++++++
> target/arm/helper.c | 14 +++++++++++---
> 2 files changed, 18 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-devel] [PATCH 13/26] target/arm: Clean excReturn bits when tail chaining, (continued)
- [Qemu-devel] [PATCH 16/26] target/arm: Move NS TBFLAG from bit 19 to bit 6, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 17/26] target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 15/26] target/arm: Handle floating point registers in exception return, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 18/26] target/arm: Set FPCCR.S when executing M-profile floating point insns, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 20/26] target/arm: New helper function arm_v7m_mmu_idx_all(), Peter Maydell, 2019/04/16
- Re: [Qemu-devel] [PATCH 20/26] target/arm: New helper function arm_v7m_mmu_idx_all(),
Richard Henderson <=
- [Qemu-devel] [PATCH 19/26] target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 21/26] target/arm: New function armv7m_nvic_set_pending_lazyfp(), Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 23/26] target/arm: Implement M-profile lazy FP state preservation, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 24/26] target/arm: Implement VLSTM for v7M CPUs with an FPU, Peter Maydell, 2019/04/16
- [Qemu-devel] [PATCH 26/26] target/arm: Enable FPU for Cortex-M4 and Cortex-M33, Peter Maydell, 2019/04/16