Re: [Qemu-devel] [PATCH v5 2/2] target/mips: Optimize ILVEV.<B|H|W|D> MSA instructions

[Richard Henderson]

On 4/2/19 11:19 PM, Philippe Mathieu-Daudé wrote:
>> +static inline void gen_ilvev_b(CPUMIPSState *env, uint32_t wd,
>> +                               uint32_t ws, uint32_t wt)
>> +{
>> +    TCGv_i64 t1 = tcg_temp_new_i64();
>> +    TCGv_i64 t2 = tcg_temp_new_i64();
>> +    const uint64_t mask = 0x00ff00ff00ff00ffULL;
>> +
>> +    tcg_gen_andi_i64(t1, msa_wr_d[wt * 2], mask);
>> +    tcg_gen_andi_i64(t2, msa_wr_d[ws * 2], mask);
>> +    tcg_gen_shli_i64(t2, t2, 8);
>> +    tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);
>> +
> 
> Richard, is it cheaper to use another register to keep the constant mask
> (here reused 4x)?
> 
> Such:
> 
>        TCGv_i64 mask = tcg_const_i64(0x00ff00ff00ff00ffULL);
> 
>        tcg_gen_and_i64(t1, msa_wr_d[wt * 2], mask);
>        tcg_gen_and_i64(t2, msa_wr_d[ws * 2], mask);
>        tcg_gen_shli_i64(t2, t2, 8);
>        tcg_gen_or_i64(msa_wr_d[wd * 2], t1, t2);

With the current state of the tcg optimizer, yes.


r~