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[Qemu-devel] [PATCH for-4.1 v2 27/36] target/unicore32: Use env_cpu, env
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH for-4.1 v2 27/36] target/unicore32: Use env_cpu, env_archcpu |
Date: |
Thu, 28 Mar 2019 13:03:55 -1000 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/unicore32/cpu.h | 5 -----
hw/unicore32/puv3.c | 2 +-
target/unicore32/helper.c | 8 ++------
target/unicore32/op_helper.c | 2 +-
target/unicore32/softmmu.c | 11 ++++-------
target/unicore32/translate.c | 26 ++------------------------
target/unicore32/ucf64_helper.c | 2 +-
7 files changed, 11 insertions(+), 45 deletions(-)
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 162e33257d..14c2d047fd 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -76,11 +76,6 @@ struct UniCore32CPU {
CPUUniCore32State env;
};
-static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
-{
- return container_of(env, UniCore32CPU, env);
-}
-
#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
index b42e600f74..132e6086ee 100644
--- a/hw/unicore32/puv3.c
+++ b/hw/unicore32/puv3.c
@@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
/* Initialize interrupt controller */
cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler,
- uc32_env_get_cpu(env), 0);
+ env_archcpu(env), 0);
dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc);
for (i = 0; i < PUV3_IRQS_NR; i++) {
irqs[i] = qdev_get_gpio_in(dev, i);
diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c
index a5ff2ddb74..19ba865482 100644
--- a/target/unicore32/helper.c
+++ b/target/unicore32/helper.c
@@ -31,8 +31,6 @@
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
/*
* movc pp.nn, rn, #imm9
* rn: UCOP_REG_D
@@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val,
uint32_t creg,
case 6:
if ((cop <= 6) && (cop >= 2)) {
/* invalid all tlb */
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
return;
}
break;
@@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x)
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (mode != ASR_MODE_USER) {
- cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
+ cpu_abort(env_cpu(env), "Tried to switch out of user mode\n");
}
}
diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c
index e0a15882d3..44ff84420e 100644
--- a/target/unicore32/op_helper.c
+++ b/target/unicore32/op_helper.c
@@ -19,7 +19,7 @@
void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
{
- CPUState *cs = CPU(uc32_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
cpu_loop_exit(cs);
diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c
index 00c7e0d028..2f31592faf 100644
--- a/target/unicore32/softmmu.c
+++ b/target/unicore32/softmmu.c
@@ -36,8 +36,6 @@
/* Map CPU modes onto saved register banks. */
static inline int bank_number(CPUUniCore32State *env, int mode)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
switch (mode) {
case ASR_MODE_USER:
case ASR_MODE_SUSR:
@@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int
mode)
case ASR_MODE_INTR:
return 4;
}
- cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
+ cpu_abort(env_cpu(env), "Bad mode %x\n", mode);
return -1;
}
@@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,
uint32_t address,
int access_type, int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
int code;
uint32_t table;
uint32_t desc;
@@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env,
uint32_t address,
*page_size = TARGET_PAGE_SIZE;
break;
default:
- cpu_abort(CPU(cpu), "wrong page type!");
+ cpu_abort(cs, "wrong page type!");
}
break;
default:
- cpu_abort(CPU(cpu), "wrong page type!");
+ cpu_abort(cs, "wrong page type!");
}
*phys_ptr = phys_addr;
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 002569ff3b..2e8341d13b 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
#define UCOP_SET_L UCOP_SET(24)
#define UCOP_SET_S UCOP_SET(24)
-#define ILLEGAL cpu_abort(CPU(cpu), \
+#define ILLEGAL cpu_abort(env_cpu(env), \
"Illegal UniCore32 instruction %x at line %d!", \
insn, __LINE__)
@@ -187,7 +187,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp, tmp2, tmp3;
if ((insn & 0xfe000000) == 0xe0000000) {
tmp2 = new_tmp();
@@ -213,7 +212,6 @@ static void disas_cp0_insn(CPUUniCore32State *env,
DisasContext *s,
static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xff003fff) == 0xe1000400) {
@@ -681,7 +679,6 @@ static inline long ucf64_reg_offset(int reg)
/* UniCore-F64 single load/store I_offset */
static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
int offset;
TCGv tmp;
TCGv addr;
@@ -728,7 +725,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env,
DisasContext *s, uint32_t in
/* UniCore-F64 load/store multiple words */
static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int i;
int j, n, freg;
TCGv tmp;
@@ -814,7 +810,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t in
/* UniCore-F64 mrc/mcr */
static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xfe0003ff) == 0xe2000000) {
@@ -879,8 +874,6 @@ static void do_ucf64_trans(CPUUniCore32State *env,
DisasContext *s, uint32_t ins
/* UniCore-F64 convert instructions */
static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -947,8 +940,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env,
DisasContext *s, uint32_t insn
/* UniCore-F64 compare instructions */
static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_SET(25)) {
ILLEGAL;
}
@@ -1027,8 +1018,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env,
DisasContext *s, uint32_t insn
/* UniCore-F64 data processing */
static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -1062,8 +1051,6 @@ static void do_ucf64_datap(CPUUniCore32State *env,
DisasContext *s, uint32_t ins
/* Disassemble an F64 instruction */
static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
if (!UCOP_SET(29)) {
if (UCOP_SET(26)) {
do_ucf64_ldst_m(env, s, insn);
@@ -1161,8 +1148,6 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
-
switch (UCOP_CPNUM) {
#ifndef CONFIG_USER_ONLY
case 0:
@@ -1177,14 +1162,13 @@ static void disas_coproc_insn(CPUUniCore32State *env,
DisasContext *s,
break;
default:
/* Unknown coprocessor. */
- cpu_abort(CPU(cpu), "Unknown coprocessor!");
+ cpu_abort(env_cpu(env), "Unknown coprocessor!");
}
}
/* data processing instructions */
static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
TCGv tmp2;
int logic_cc;
@@ -1418,7 +1402,6 @@ static void do_mult(CPUUniCore32State *env, DisasContext
*s, uint32_t insn)
/* miscellaneous instructions */
static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
TCGv tmp;
@@ -1544,7 +1527,6 @@ static void do_ldst_ir(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* SWP instruction */
static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
TCGv tmp2;
@@ -1572,7 +1554,6 @@ static void do_swap(CPUUniCore32State *env, DisasContext
*s, uint32_t insn)
/* load/store hw/sb */
static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t
insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
@@ -1625,7 +1606,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
@@ -1767,7 +1747,6 @@ static void do_ldst_m(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
/* branch (and link) */
static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
int32_t offset;
TCGv tmp;
@@ -1797,7 +1776,6 @@ static void do_branch(CPUUniCore32State *env,
DisasContext *s, uint32_t insn)
static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int insn;
insn = cpu_ldl_code(env, s->pc);
diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helper.c
index fad3fa6618..e078e84437 100644
--- a/target/unicore32/ucf64_helper.c
+++ b/target/unicore32/ucf64_helper.c
@@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
+ UniCore32CPU *cpu = env_archcpu(env);
int i;
uint32_t changed;
--
2.17.1
- [Qemu-devel] [PATCH for-4.1 v2 26/36] target/tricore: Use env_cpu, (continued)
- [Qemu-devel] [PATCH for-4.1 v2 26/36] target/tricore: Use env_cpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 32/36] cpu: Move icount_decr to CPUNegativeOffsetState, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 21/36] target/riscv: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 22/36] target/s390x: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 17/36] target/moxie: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 20/36] target/ppc: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 14/36] target/m68k: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 13/36] target/lm32: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 10/36] target/cris: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 25/36] target/tilegx: Use env_cpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 27/36] target/unicore32: Use env_cpu, env_archcpu,
Richard Henderson <=
- [Qemu-devel] [PATCH for-4.1 v2 12/36] target/i386: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 08/36] target/alpha: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 15/36] target/microblaze: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 02/36] tcg: Split out target/arch/cpu-param.h, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 04/36] cpu: Define CPUArchState with typedef, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 16/36] target/mips: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 11/36] target/hppa: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 07/36] cpu: Introduce env_archcpu, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 05/36] cpu: Define ArchCPU, Richard Henderson, 2019/03/28
- [Qemu-devel] [PATCH for-4.1 v2 01/36] tcg: Fold CPUTLBWindow into CPUTLBDesc, Richard Henderson, 2019/03/28