Re: [Qemu-devel] [PULL] A Single RISC-V Patch for 4.0-rc1

[Peter Maydell]

On Tue, 26 Mar 2019 at 06:54, Palmer Dabbelt <address@hidden> wrote:
>
> The following changes since commit 62a172e6a77d9072bb1a18f295ce0fcf4b90a4f2:
>
>   Update version for v4.0.0-rc0 release (2019-03-19 17:17:22 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc1
>
> for you to fetch changes up to f17e02cd3731bdfe2942d1d0b2a92f26da02408c:
>
>   target/riscv: Zero extend the inputs of divuw and remuw (2019-03-22 
> 00:26:39 -0700)
>
> ----------------------------------------------------------------
> A Single RISC-V Patch for 4.0-rc1
>
> If this is too late I'm OK with it being in rc2, but it fixes a concrete
> regression and nobody has complained yet so I'd prefer it to be in rc1
> if possible.
>
> The fix is to zero-extend the inputs to DIVUW and REMUW, which was
> exposed by the GCC test suite.
>
> ----------------------------------------------------------------
> Palmer Dabbelt (1):
>       target/riscv: Zero extend the inputs of divuw and remuw

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM