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[Qemu-devel] [PATCH v2 5/7] target/mips: Eliminate unreachable case for
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH v2 5/7] target/mips: Eliminate unreachable case for MSA instructions copy_u |
Date: |
Mon, 25 Mar 2019 15:52:44 +0100 |
From: Mateja Marjanovic <address@hidden>
The copy_u instruction doesn't support doublewords, and supports
words only if the CPU is MIPS64 [1] (page 138), for MIPS32 it
supports only byte and halfword [2] (page 138).
[1] MIPS Architecture for Programmers
Volume IV-j: The MIPS64 SIMD
Architecture Module
[2] MIPS Architecture for Programmers
Volume IV-j: The MIPS32 SIMD
Architecture Module
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/msa_helper.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index ac5d41e..f368f79 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1482,13 +1482,10 @@ void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t
df, uint32_t rd,
case DF_HALF:
env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
break;
+#ifdef TARGET_MIPS64
case DF_WORD:
env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
break;
-#ifdef TARGET_MIPS64
- case DF_DOUBLE:
- env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
- break;
#endif
default:
assert(0);
--
2.7.4
[Qemu-devel] [PATCH v2 3/7] target/mips: Fix copy_u.<b|h|w> for MIPS big endian host, Mateja Marjanovic, 2019/03/25
[Qemu-devel] [PATCH v2 6/7] target/mips: Eliminate unreachable case for MSA instructions insert, Mateja Marjanovic, 2019/03/25