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[Qemu-devel] [PATCH RFC v5 12/12] include/hw/regiserfields.h: Add 8bit a
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH RFC v5 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers |
Date: |
Mon, 25 Mar 2019 18:00:47 +0900 |
Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.
Signed-off-by: Yoshinori Sato <address@hidden>
---
include/hw/registerfields.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..f6bf911990 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
enum { A_ ## reg = (addr) }; \
enum { R_ ## reg = (addr) / 4 };
+#define REG8(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr) \
+ enum { A_ ## reg = (addr) }; \
+ enum { R_ ## reg = (addr) / 2 };
+
/* Define SHIFT, LENGTH and MASK constants for a field within a register */
/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -40,6 +48,8 @@
#define FIELD_EX64(storage, reg, field) \
extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX8 FIELD_EX32
+#define FIELD_EX16 FIELD_EX32
/* Extract a field from an array of registers */
#define ARRAY_FIELD_EX32(regs, reg, field) \
--
2.11.0
- [Qemu-devel] [PATCH RFC v4 02/12] target/rx: TCG helper, (continued)
- [Qemu-devel] [PATCH RFC v4 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/03/20
- [Qemu-devel] [PATCH RFC v4 07/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/03/20
- [Qemu-devel] [PATCH RFC v4 08/12] hw/char: RX62N serical communication interface (SCI), Yoshinori Sato, 2019/03/20
- [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Yoshinori Sato, 2019/03/20
- Re: [Qemu-devel] [PATCH RFC v4 01/12] target/rx: TCG translation, Richard Henderson, 2019/03/21
- Re: [Qemu-devel] [PATCH RFC v4 00/12] Add RX archtecture support, no-reply, 2019/03/20
- [Qemu-devel] [PATCH RFC v5 00/12] Add RX archtecture support, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers,
Yoshinori Sato <=
- [Qemu-devel] [PATCH RFC v5 06/12] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 05/12] target/rx: Miscellaneous files, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 08/12] hw/char: RX62N serical communication interface (SCI), Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 09/12] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 02/12] target/rx: TCG helper, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 11/12] MAINTAINERS: Add RX, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 04/12] target/rx: RX disassembler, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 10/12] Add rx-softmmu, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 07/12] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/03/25
- [Qemu-devel] [PATCH RFC v5 03/12] target/rx: CPU definition, Yoshinori Sato, 2019/03/25