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[Qemu-devel] [PATCH 23/35] target/sh4: Use env_cpu, env_archcpu
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 23/35] target/sh4: Use env_cpu, env_archcpu |
Date: |
Sat, 23 Mar 2019 12:09:13 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/sh4/cpu.h | 5 -----
linux-user/sh4/cpu_loop.c | 2 +-
target/sh4/helper.c | 26 ++++++++++++--------------
target/sh4/op_helper.c | 9 +++------
4 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 95094a517a..1f94e7bf7b 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -207,11 +207,6 @@ struct SuperHCPU {
CPUSH4State env;
};
-static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
-{
- return container_of(env, SuperHCPU, env);
-}
-
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
index 47e54b9b61..677c5a461c 100644
--- a/linux-user/sh4/cpu_loop.c
+++ b/linux-user/sh4/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 2ff0cf4060..5240da715e 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -238,8 +238,6 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
static int itlb_replacement(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0;
}
@@ -252,7 +250,7 @@ static int itlb_replacement(CPUSH4State * env)
if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3;
}
- cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
+ cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -308,7 +306,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
itlb = itlb_replacement(env);
ientry = &env->itlb[itlb];
if (ientry->v) {
- tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
+ tlb_flush_page(env_cpu(env), ientry->vpn << 10);
}
*ientry = env->utlb[utlb];
update_itlb_use(env, itlb);
@@ -533,14 +531,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
void cpu_load_tlb(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
+ CPUState *cs = env_cpu(env);
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(cpu), address);
+ tlb_flush_page(cs, address);
}
/* Take values into cpu status from registers. */
@@ -563,7 +561,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */
break;
default:
- cpu_abort(CPU(cpu), "Unhandled load_tlb");
+ cpu_abort(cs, "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
@@ -590,7 +588,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->v = 0;
}
- tlb_flush(CPU(sh_env_get_cpu(s)));
+ tlb_flush(env_cpu(s));
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
@@ -616,7 +614,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr
addr,
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->asid = asid;
entry->vpn = vpn;
@@ -658,7 +656,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr
addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
@@ -711,7 +709,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr
addr,
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Multiple TLB Exception */
cs->exception_index = 0x140;
@@ -743,14 +741,14 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s,
hwaddr addr,
}
if (needs_tlb_flush) {
- tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
+ tlb_flush_page(env_cpu(s), vpn << 10);
}
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
if (entry->v) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
@@ -805,7 +803,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr
addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 12fba6fc78..11cb68cc1c 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -58,10 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
- /* XXXXX */
- cpu_abort(CPU(cpu), "Unhandled ldtlb");
+ cpu_abort(env_cpu(env), "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif
@@ -70,7 +67,7 @@ void helper_ldtlb(CPUSH4State *env)
static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
uintptr_t retaddr)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit_restore(cs, retaddr);
@@ -103,7 +100,7 @@ void helper_debug(CPUSH4State *env)
void helper_sleep(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
env->in_sleep = 1;
--
2.17.1
- [Qemu-devel] [PATCH 27/35] target/unicore32: Use env_cpu, env_archcpu, (continued)
- [Qemu-devel] [PATCH 27/35] target/unicore32: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 35/35] tcg/arm: Use LDRD to load tlb mask+table, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 28/35] target/xtensa: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 20/35] target/ppc: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 34/35] tcg/aarch64: Use LDP to load tlb mask+table, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 22/35] target/s390x: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 17/35] target/moxie: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 19/35] target/openrisc: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 18/35] target/nios2: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 24/35] target/sparc: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 23/35] target/sh4: Use env_cpu, env_archcpu,
Richard Henderson <=
- [Qemu-devel] [PATCH 21/35] target/riscv: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 26/35] target/tricore: Use env_cpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 14/35] target/m68k: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 15/35] target/microblaze: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 13/35] target/lm32: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 12/35] target/i386: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 09/35] target/arm: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 11/35] target/hppa: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 10/35] target/cris: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 08/35] target/alpha: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23