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[Qemu-devel] [PATCH 29/35] cpu: Move ENV_OFFSET to exec/gen-icount.h
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 29/35] cpu: Move ENV_OFFSET to exec/gen-icount.h |
Date: |
Sat, 23 Mar 2019 12:09:19 -0700 |
Now that we have ArchCPU, we can define this generically,
in the one place that needs it.
Signed-off-by: Richard Henderson <address@hidden>
---
include/exec/gen-icount.h | 2 ++
target/alpha/cpu.h | 1 -
target/arm/cpu.h | 2 --
target/cris/cpu.h | 1 -
target/hppa/cpu.h | 1 -
target/i386/cpu.h | 1 -
target/lm32/cpu.h | 1 -
target/m68k/cpu.h | 1 -
target/microblaze/cpu.h | 1 -
target/mips/cpu.h | 1 -
target/moxie/cpu.h | 1 -
target/nios2/cpu.h | 1 -
target/openrisc/cpu.h | 1 -
target/ppc/cpu.h | 1 -
target/riscv/cpu.h | 2 --
target/s390x/cpu.h | 1 -
target/sh4/cpu.h | 1 -
target/sparc/cpu.h | 1 -
target/tilegx/cpu.h | 1 -
target/tricore/cpu.h | 1 -
target/unicore32/cpu.h | 1 -
target/xtensa/cpu.h | 2 --
22 files changed, 2 insertions(+), 24 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 24f7991781..9cfa6ccce5 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -5,6 +5,8 @@
/* Helpers for instruction counting code generation. */
+#define ENV_OFFSET offsetof(ArchCPU, env)
+
static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb)
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e22518871a..93919bbaa2 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -273,7 +273,6 @@ struct AlphaCPU {
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_alpha_cpu;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5797927992..41b76eed4e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -907,8 +907,6 @@ void arm_cpu_post_init(Object *obj);
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
-#define ENV_OFFSET offsetof(ARMCPU, env)
-
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_arm_cpu;
#endif
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 6111dbb14c..b87a559137 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -183,7 +183,6 @@ struct CRISCPU {
CPUCRISState env;
};
-#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_cris_cpu;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 1387066324..65986dacbf 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -222,7 +222,6 @@ struct HPPACPU {
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7ff5ab77c1..c5351bea7e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1477,7 +1477,6 @@ struct X86CPU {
int32_t hv_max_vps;
};
-#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY
extern struct VMStateDescription vmstate_x86_cpu;
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 69beb16972..deb83153b3 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -195,7 +195,6 @@ struct LM32CPU {
uint32_t features;
};
-#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_lm32_cpu;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index eb3048914e..2b180cf18d 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -163,7 +163,6 @@ struct M68kCPU {
CPUM68KState env;
};
-#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index a9748d57ad..ff3abb61af 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -310,7 +310,6 @@ struct MicroBlazeCPU {
CPUMBState env;
};
-#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 914cc26c21..49c226b587 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1051,7 +1051,6 @@ struct MIPSCPU {
CPUMIPSState env;
};
-#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 71e7cf0f08..00b1486659 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -90,7 +90,6 @@ typedef struct MoxieCPU {
CPUMoxieState env;
} MoxieCPU;
-#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 3fc27ead81..39a2471b18 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -193,7 +193,6 @@ typedef struct Nios2CPU {
uint32_t fast_tlb_miss_addr;
} Nios2CPU;
-#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 853cf633e7..ad2118b599 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -317,7 +317,6 @@ typedef struct OpenRISCCPU {
} OpenRISCCPU;
-#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
void openrisc_cpu_do_interrupt(CPUState *cpu);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c3fe154979..038e2499ed 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1191,7 +1191,6 @@ struct PowerPCCPU {
int32_t mig_slb_nr;
};
-#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c18dd5eb24..9e71297ca7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -229,8 +229,6 @@ extern const char * const riscv_fpr_regnames[];
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
-#define ENV_OFFSET offsetof(RISCVCPU, env)
-
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 372d4c198f..3a6a5ada86 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,7 +163,6 @@ struct S390CPU {
uint32_t irqstate_saved_size;
};
-#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_s390_cpu;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 1f94e7bf7b..02269c09b8 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -207,7 +207,6 @@ struct SuperHCPU {
CPUSH4State env;
};
-#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index bf6f63d029..02e40d381b 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -532,7 +532,6 @@ struct SPARCCPU {
CPUSPARCState env;
};
-#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_sparc_cpu;
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7f8fe7c513..643b7dbd17 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -138,7 +138,6 @@ typedef struct TileGXCPU {
CPUTLGState env;
} TileGXCPU;
-#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 9ea5060a87..9e60ef981b 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -208,7 +208,6 @@ struct TriCoreCPU {
CPUTriCoreState env;
};
-#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 14c2d047fd..12b8268f7b 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -76,7 +76,6 @@ struct UniCore32CPU {
CPUUniCore32State env;
};
-#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d5465c2853..6fddac3a2b 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -529,8 +529,6 @@ struct XtensaCPU {
CPUXtensaState env;
};
-#define ENV_OFFSET offsetof(XtensaCPU, env)
-
int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int size,
int mmu_idx);
--
2.17.1
- [Qemu-devel] [PATCH for-4.1 00/35] tcg: Move the softmmu tlb to CPUNegativeOffsetState, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 16/35] target/mips: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 30/35] cpu: Introduce CPUNegativeOffsetState, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 32/35] cpu: Move the softmmu tlb to CPUNegativeOffsetState, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 29/35] cpu: Move ENV_OFFSET to exec/gen-icount.h,
Richard Henderson <=
- [Qemu-devel] [PATCH 25/35] target/tilegx: Use env_cpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 33/35] cpu: Remove CPU_COMMON, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 31/35] cpu: Move icount_decr to CPUNegativeOffsetState, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 27/35] target/unicore32: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 35/35] tcg/arm: Use LDRD to load tlb mask+table, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 28/35] target/xtensa: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23
- [Qemu-devel] [PATCH 20/35] target/ppc: Use env_cpu, env_archcpu, Richard Henderson, 2019/03/23