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Re: [Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw a


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw
Date: Thu, 21 Mar 2019 10:46:20 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0

On 3/21/19 7:59 AM, Palmer Dabbelt wrote:
> While running the GCC test suite against 4.0.0-rc0, Kito found a
> regression introduced by the decodetree conversion that caused divuw and
> remuw to sign-extend their inputs.  The ISA manual says they are
> supposed to be zero extended:
> 
>     DIVW and DIVUW instructions are only valid for RV64, and divide the
>     lower 32 bits of rs1 by the lower 32 bits of rs2, treating them as
>     signed and unsigned integers respectively, placing the 32-bit
>     quotient in rd, sign-extended to 64 bits. REMW and REMUW
>     instructions are only valid for RV64, and provide the corresponding
>     signed and unsigned remainder operations respectively.  Both REMW
>     and REMUW always sign-extend the 32-bit result to 64 bits, including
>     on a divide by zero.
> 
> Here's Kito's reduced test case from the GCC test suite
> 
>     unsigned calc_mp(unsigned mod)
>     {
>          unsigned a,b,c;
>          c=-1;
>          a=c/mod;
>          b=0-a*mod;
>          if (b > mod) { a += 1; b-=mod; }
>          return b;
>     }
> 
>     int main(int argc, char *argv[])
>     {
>          unsigned x = 1234;
>          unsigned y = calc_mp(x);
> 
>          if ((sizeof (y) == 4 && y != 680)
>       || (sizeof (y) == 2 && y != 134))
>     abort ();
>          exit (0);
>     }
> 
> I haven't done any other testing on this, but it does fix the test case.
> 
> Signed-off-by: Palmer Dabbelt <address@hidden>
> ---
>  target/riscv/insn_trans/trans_rvm.inc.c |  4 ++--
>  target/riscv/translate.c                | 21 +++++++++++++++++++++
>  2 files changed, 23 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <address@hidden>


r~



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