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[Qemu-devel] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority b
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority base offset |
Date: |
Thu, 21 Mar 2019 00:46:27 +0000 |
According to the FE31 manual the PLIC source priority address starts at
an offset of 0x04 and not 0x00.
Signed-off-by: Alistair Francis <address@hidden>
---
include/hw/riscv/sifive_e.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 7b6d8aed96..f715f8606f 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -70,7 +70,7 @@ enum {
#define SIFIVE_E_PLIC_HART_CONFIG "M"
#define SIFIVE_E_PLIC_NUM_SOURCES 127
#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
-#define SIFIVE_E_PLIC_PRIORITY_BASE 0x0
+#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
--
2.21.0
[Qemu-devel] [PATCH for 4.0 v1 3/5] riscv: sifive_e: Fix PLIC priority base offset,
Alistair Francis <=
Re: [Qemu-devel] [PATCH for 4.0 v1 0/5] Update the QEMU PLIC addresses, Alistair Francis, 2019/03/26
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