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[Qemu-devel] [PULL 5/7] ppc/pnv: Fix variable size in pnv_psi_power9_irq
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 5/7] ppc/pnv: Fix variable size in pnv_psi_power9_irq_set() |
Date: |
Tue, 19 Mar 2019 21:06:43 +1100 |
From: Greg Kurz <address@hidden>
PSI registers are 64-bit.
Spotted by Coverity: CID 1399704
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_psi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 5a923e4151..5345c8389e 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -786,7 +786,7 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
{
- uint32_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
+ uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
if (irq > PSIHB9_NUM_IRQS) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
--
2.20.1
- [Qemu-devel] [PULL 0/7] ppc-for-4.0 queue 20190319, David Gibson, 2019/03/19
- [Qemu-devel] [PULL 1/7] spapr: Correctly set LPCR[GTSE] in H_REGISTER_PROCESS_TABLE, David Gibson, 2019/03/19
- [Qemu-devel] [PULL 7/7] spapr: Remove NULL checks on error_propagate() calls, David Gibson, 2019/03/19
- [Qemu-devel] [PULL 6/7] ppc/xics/spapr: Fix H_IPOLL implementation, David Gibson, 2019/03/19
- [Qemu-devel] [PULL 5/7] ppc/pnv: Fix variable size in pnv_psi_power9_irq_set(),
David Gibson <=
- [Qemu-devel] [PULL 3/7] MAINTAINERS: PPC: add a PowerNV machine entry, David Gibson, 2019/03/19
- [Qemu-devel] [PULL 4/7] ppc/pnv: Use local_err variable in pnv_chip_power9_intc_create(), David Gibson, 2019/03/19
- [Qemu-devel] [PULL 2/7] ppc/pnv: update skiboot to commit 261ca8e779e5., David Gibson, 2019/03/19
- Re: [Qemu-devel] [PULL 0/7] ppc-for-4.0 queue 20190319, Peter Maydell, 2019/03/19