[Qemu-devel] [PATCH for-4.1 v2 00/13] tcg/ppc: Add vector opcodes

[Richard Henderson]

Version 2 does not require VSX, and works with just Altivec.
But the last 3 patches incrementally add Power7/8/9 instructions.

I've tested this vs aa64 risu on power7 big-endian and power9
little-endian, so all of the easy bugs are out.  ;-)


r~


Richard Henderson (13):
  tcg: Assert fixed_reg is read-only
  tcg: Return bool success from tcg_out_mov
  tcg: Support cross-class moves without instruction support
  tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded
  target/arm: Fill in .opc for cmtst_op
  tcg/ppc: Initial backend support for Altivec
  tcg: Add INDEX_op_dup_mem_vec
  tcg/ppc: Implement INDEX_op_dupm_vec
  tcg/ppc: Support vector shift by immediate
  tcg/ppc: Support vector multiply
  tcg/ppc: Update vector support to v2.06
  tcg/ppc: Update vector support to v2.07
  tcg/ppc: Update vector support to v3.00

 tcg/aarch64/tcg-target.h     |    1 +
 tcg/i386/tcg-target.h        |    1 +
 tcg/ppc/tcg-target.h         |   34 +-
 tcg/ppc/tcg-target.opc.h     |   11 +
 tcg/tcg-op.h                 |    1 +
 tcg/tcg-opc.h                |    1 +
 tcg/tcg.h                    |    1 +
 target/arm/translate.c       |    4 +
 tcg/aarch64/tcg-target.inc.c |    5 +-
 tcg/arm/tcg-target.inc.c     |    7 +-
 tcg/i386/tcg-target.inc.c    |    5 +-
 tcg/mips/tcg-target.inc.c    |    3 +-
 tcg/ppc/tcg-target.inc.c     | 1039 ++++++++++++++++++++++++++++++++--
 tcg/riscv/tcg-target.inc.c   |    5 +-
 tcg/s390/tcg-target.inc.c    |    3 +-
 tcg/sparc/tcg-target.inc.c   |    3 +-
 tcg/tcg-op-gvec.c            |   88 +--
 tcg/tcg-op-vec.c             |   60 +-
 tcg/tcg.c                    |  120 ++--
 tcg/tci/tcg-target.inc.c     |    3 +-
 20 files changed, 1212 insertions(+), 183 deletions(-)
 create mode 100644 tcg/ppc/tcg-target.opc.h

-- 
2.17.2