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[Qemu-devel] [PULL 5/5] target/arm: Check access permission to ADDVL/ADD
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 5/5] target/arm: Check access permission to ADDVL/ADDPL/RDVL |
Date: |
Fri, 15 Mar 2019 11:39:06 +0000 |
From: Amir Charif <address@hidden>
These instructions do not trap when SVE is disabled in EL0,
causing them to be executed with wrong size information.
Signed-off-by: Amir Charif <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added 'target/arm' prefix to subject]
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 3a2eb515664..245cd826217 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -943,24 +943,30 @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr
*a)
static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
{
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
- tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
+ }
return true;
}
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
{
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
- tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
+ tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
+ }
return true;
}
static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
{
- TCGv_i64 reg = cpu_reg(s, a->rd);
- tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
+ if (sve_access_check(s)) {
+ TCGv_i64 reg = cpu_reg(s, a->rd);
+ tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
+ }
return true;
}
--
2.20.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2019/03/15
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2019/03/15
- [Qemu-devel] [PULL 3/5] target/arm: change arch timer registers access permission, Peter Maydell, 2019/03/15
- [Qemu-devel] [PULL 5/5] target/arm: Check access permission to ADDVL/ADDPL/RDVL,
Peter Maydell <=
- [Qemu-devel] [PULL 1/5] hw/intc/bcm2836_control: Implement local timer, Peter Maydell, 2019/03/15
- [Qemu-devel] [PULL 4/5] hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number, Peter Maydell, 2019/03/15
- [Qemu-devel] [PULL 2/5] hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values, Peter Maydell, 2019/03/15