[Qemu-devel] [PATCH v5 0/5] RISC-V: Add gdb xml files and gdbstub support

[Chih-Min Chao]

This is the 5th version of the patch set, based on the Jim's previous work,
     http://lists.nongnu.org/archive/html/qemu-riscv/2019-02/msg00059.html

    v4 -> v5:
       - rebase 7074ab1
       - update the register xml files to gdb 8.3 
       - refine the fpu control registers, fflags/frm/fcsr index calculation
       - fix the csr offset calculcation because of tne regnum field in fpu
         xml file introducing one useless number

Jim Wilson (5):
  RISC-V: Add 32-bit gdb xml files.
  RISC-V: Add 64-bit gdb xml files.
  RISC-V: Fixes to CSR_* register macros.
  RISC-V: Add debug support for accessing CSRs.
  RISC-V: Add hooks to use the gdb xml files.

 configure                   |   2 +
 gdb-xml/riscv-32bit-cpu.xml |  47 ++++++
 gdb-xml/riscv-32bit-csr.xml | 250 +++++++++++++++++++++++++++++++
 gdb-xml/riscv-32bit-fpu.xml |  50 +++++++
 gdb-xml/riscv-64bit-cpu.xml |  47 ++++++
 gdb-xml/riscv-64bit-csr.xml | 250 +++++++++++++++++++++++++++++++
 gdb-xml/riscv-64bit-fpu.xml |  56 +++++++
 target/riscv/cpu.c          |   9 +-
 target/riscv/cpu.h          |   7 +
 target/riscv/cpu_bits.h     |  35 ++++-
 target/riscv/csr.c          |  32 +++-
 target/riscv/gdbstub.c      | 350 ++++++++++++++++++++++++++++++++++++++++++--
 12 files changed, 1114 insertions(+), 21 deletions(-)
 create mode 100644 gdb-xml/riscv-32bit-cpu.xml
 create mode 100644 gdb-xml/riscv-32bit-csr.xml
 create mode 100644 gdb-xml/riscv-32bit-fpu.xml
 create mode 100644 gdb-xml/riscv-64bit-cpu.xml
 create mode 100644 gdb-xml/riscv-64bit-csr.xml
 create mode 100644 gdb-xml/riscv-64bit-fpu.xml

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2.7.4