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[Qemu-devel] [PULL 11/11] target/hppa: exit TB if either Data or Instruc
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 11/11] target/hppa: exit TB if either Data or Instruction TLB changes |
Date: |
Tue, 12 Mar 2019 09:19:04 -0700 |
From: Sven Schnelle <address@hidden>
The current code assumes that we don't need to exit the TB
if a Data Cache Flush or Insert has happend. However, as we
have a shared Data/Instruction TLB, a Data cache flush also
flushes Instruction TLB entries, and a Data cache TLB insert
might also evict a Instruction TLB entry.
So exit the TB in all cases if Instruction translation is enabled.
Signed-off-by: Sven Schnelle <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/hppa/translate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 70a7cd4a89..35c504087f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2482,9 +2482,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
gen_helper_itlbp(cpu_env, addr, reg);
}
- /* Exit TB for ITLB change if mmu is enabled. This *should* not be
- the case, since the OS TLB fill handler runs with mmu disabled. */
- if (!a->data && (ctx->tb_flags & PSW_C)) {
+ /* Exit TB for TLB change if mmu is enabled. */
+ if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
@@ -2511,7 +2510,7 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
}
/* Exit TB for TLB change if mmu is enabled. */
- if (!a->data && (ctx->tb_flags & PSW_C)) {
+ if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
--
2.17.2
- [Qemu-devel] [PULL 01/11] target/hppa: Check for page crossings in use_goto_tb, (continued)
- [Qemu-devel] [PULL 01/11] target/hppa: Check for page crossings in use_goto_tb, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 02/11] target/hppa: fix overwriting source reg in addb, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 03/11] target/hppa: fix TLB handling for page 0, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 05/11] target/hppa: add TLB trace events, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 04/11] target/hppa: report ITLB_EXCP_MISS for ITLB misses, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 06/11] target/hppa: remove PSW I/R/Q bit check, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 08/11] target/hppa: fix b,gate instruction, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 07/11] target/hppa: ignore DIAG opcode, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 09/11] target/hppa: allow multiple itlbp without itlba, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 10/11] target/hppa: add TLB protection id check, Richard Henderson, 2019/03/12
- [Qemu-devel] [PULL 11/11] target/hppa: exit TB if either Data or Instruction TLB changes,
Richard Henderson <=
- Re: [Qemu-devel] [PULL 00/11] target/hppa patch queue, no-reply, 2019/03/12
- Re: [Qemu-devel] [PULL 00/11] target/hppa patch queue, Peter Maydell, 2019/03/13