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[Qemu-devel] [PULL 17/62] target/ppc/spapr: Clear partition table entry
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 17/62] target/ppc/spapr: Clear partition table entry when allocating hash table |
Date: |
Tue, 12 Mar 2019 19:52:31 +1100 |
From: Suraj Jitindar Singh <address@hidden>
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
H_REGISTER_PROCESS_TABLE there will be a mismatch between then flags
and the value in spapr->patb_entry, and the call will fail. The guest
will then panic:
Failed to register process table (rc=-4)
kernel BUG at arch/powerpc/platforms/pseries/lpar.c:959
The result being that it isn't possible to boot a hash guest on a P9
system.
Also fix a bug in the flags parsing in h_register_process_table() which
was introduced by the same patch, and simplify the handling to make it
less likely that errors will be introduced in the future. The effect
would have been setting the host radix bit LPCR_HR for a hash guest
using process tables, which currently isn't supported and so couldn't
have been triggered.
Fixes: 00fd075e18 "target/ppc/spapr: Set LPCR:HR when using Radix mode"
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_hcall.c | 12 ++++++++----
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 946bbcf9ee..755056875c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1632,6 +1632,7 @@ void spapr_reallocate_hpt(sPAPRMachineState *spapr, int
shift,
}
}
/* We're setting up a hash table, so that means we're not radix */
+ spapr->patb_entry = 0;
spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 15bdd30a12..50af3c0a62 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -1339,6 +1339,7 @@ static target_ulong h_register_process_table(PowerPCCPU
*cpu,
target_ulong proc_tbl = args[1];
target_ulong page_size = args[2];
target_ulong table_size = args[3];
+ target_ulong update_lpcr = 0;
uint64_t cproc;
if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
@@ -1394,10 +1395,13 @@ static target_ulong h_register_process_table(PowerPCCPU
*cpu,
spapr->patb_entry = cproc; /* Save new process table */
/* Update the UPRT, HR and GTSE bits in the LPCR for all cpus */
- spapr_set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ?
- (LPCR_UPRT | LPCR_HR) : 0) |
- ((flags & FLAG_GTSE) ? LPCR_GTSE : 0),
- LPCR_UPRT | LPCR_HR | LPCR_GTSE);
+ if (flags & FLAG_RADIX) /* Radix must use process tables, also set HR
*/
+ update_lpcr |= (LPCR_UPRT | LPCR_HR);
+ else if (flags & FLAG_HASH_PROC_TBL) /* Hash with process tables */
+ update_lpcr |= LPCR_UPRT;
+ if (flags & FLAG_GTSE) /* Guest translation shootdown enable */
+ update_lpcr |= FLAG_GTSE;
+ spapr_set_all_lpcrs(update_lpcr, LPCR_UPRT | LPCR_HR | LPCR_GTSE);
if (kvm_enabled()) {
return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
--
2.20.1
- [Qemu-devel] [PULL 59/62] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), (continued)
- [Qemu-devel] [PULL 59/62] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 56/62] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 62/62] vfio: Make vfio_get_region_info_cap public, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 54/62] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 61/62] Suppress test warnings about missing Spectre/Meltdown mitigations with TCG, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 50/62] ppc/pnv: add a OCC model class, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 48/62] ppc/pnv: add a LPC Controller model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 60/62] spapr: Use CamelCase properly, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 00/62] ppc-for-4.0 queue 20190312, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 12/62] target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 17/62] target/ppc/spapr: Clear partition table entry when allocating hash table,
David Gibson <=
- [Qemu-devel] [PULL 22/62] ppc: externalize ppc_get_vcpu_by_pir(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 24/62] ppc/pnv: export the xive_router_notify() routine, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 20/62] PPC: E500: Add FSL I2C controller and integrate RTC with it, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 06/62] target/ppc: Implement large decrementer support for TCG, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 21/62] ppc/xive: hardwire the Physical CAM line of the thread context, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 13/62] target/ppc: Move exception vector offset computation into a function, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 10/62] target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 05/62] target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 19/62] target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 25/62] ppc/pnv: change the CPU machine_data presenter type to Object *, David Gibson, 2019/03/12