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[Qemu-devel] [PULL 45/62] ppc/pnv: lpc: fix OPB address ranges
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 45/62] ppc/pnv: lpc: fix OPB address ranges |
Date: |
Tue, 12 Mar 2019 19:54:45 +1100 |
From: Cédric Le Goater <address@hidden>
The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.
The mapping addresses of each register range are correct but the sizes
are too large. Fix the sizes and define the OPB Arbitrer range to fill
the gap between the OPB Master registers and the LPC HOST Controller
registers.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_lpc.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 9b18ce55e3..547be609ca 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -89,10 +89,11 @@ enum {
#define LPC_FW_OPB_SIZE 0x10000000
#define LPC_OPB_REGS_OPB_ADDR 0xc0010000
-#define LPC_OPB_REGS_OPB_SIZE 0x00002000
+#define LPC_OPB_REGS_OPB_SIZE 0x00000060
+#define LPC_OPB_REGS_OPBA_ADDR 0xc0011000
+#define LPC_OPB_REGS_OPBA_SIZE 0x00000008
#define LPC_HC_REGS_OPB_ADDR 0xc0012000
-#define LPC_HC_REGS_OPB_SIZE 0x00001000
-
+#define LPC_HC_REGS_OPB_SIZE 0x00000100
static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int
xscom_offset)
{
--
2.20.1
- [Qemu-devel] [PULL 41/62] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, (continued)
- [Qemu-devel] [PULL 41/62] mac_oldworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 36/62] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 39/62] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 42/62] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 47/62] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 49/62] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 38/62] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 46/62] ppc/pnv: add a LPC Controller class model, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 51/62] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 53/62] ppc/pnv: POWER9 XSCOM quad support, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 45/62] ppc/pnv: lpc: fix OPB address ranges,
David Gibson <=
- [Qemu-devel] [PULL 16/62] PPC: E500: Update u-boot to v2019.01, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 52/62] ppc/pnv: extend XSCOM core support for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 58/62] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 57/62] target/ppc: add HV support for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 55/62] ppc/pnv: add more dummy XSCOM addresses, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 59/62] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/12
- [Qemu-devel] [PULL 56/62] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 62/62] vfio: Make vfio_get_region_info_cap public, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 54/62] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/12
- [Qemu-devel] [PULL 61/62] Suppress test warnings about missing Spectre/Meltdown mitigations with TCG, David Gibson, 2019/03/12