Re: [Qemu-devel] [PATCH 4/6] target/m68k: Optimize get_sr() using deposit_i32()

[Richard Henderson]

On 3/9/19 4:34 PM, Philippe Mathieu-Daudé wrote:
>  static TCGv gen_get_sr(DisasContext *s)
>  {
> -    TCGv ccr;
> -    TCGv sr;
> +    TCGv dest;
>  
> -    ccr = gen_get_ccr(s);
> -    sr = tcg_temp_new();
> -    tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
> -    tcg_gen_or_i32(sr, sr, ccr);
> -    tcg_temp_free(ccr);
> -    return sr;
> +    dest = gen_get_ccr(s);
> +    tcg_gen_deposit_i32(dest, dest, QREG_SR, 5, 11);
> +    return dest;

Err.. there's no shift of QREG_SR by 5 in the original.
I think you meant

  tcg_gen_deposit_i32(dest, QREG_SR, dest, 0, 5);

But I'd be surprised if QREG_SR even has those bits set,
and we could elide the ANDI entirely, making this just an OR.


r~