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[Qemu-devel] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp using deposit
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp using deposit_i64() |
Date: |
Sun, 10 Mar 2019 19:27:02 +1100 |
From: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 30d8aabd92..508e9199c8 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1587,8 +1587,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
get_cpu_vsrh(t1, xB(ctx->opcode));
- tcg_gen_andi_i64(rt, t1, 0x000FFFFFFFFFFFFF);
- tcg_gen_or_i64(rt, rt, t0);
+ tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
@@ -1624,8 +1623,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
tcg_gen_movi_i64(t0, 0x0001000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_andi_i64(xth, xbh, 0x0000FFFFFFFFFFFF);
- tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
tcg_gen_mov_i64(xtl, xbl);
set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
@@ -1814,16 +1812,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
- tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
set_cpu_vsrh(xT(ctx->opcode), xth);
tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
- tcg_gen_andi_i64(xtl, xbl, 0x000FFFFFFFFFFFFF);
- tcg_gen_or_i64(xtl, xtl, t0);
+ tcg_gen_deposit_i64(xth, t0, xbl, 0, 52);
set_cpu_vsrl(xT(ctx->opcode), xtl);
tcg_temp_free_i64(t0);
--
2.20.1
- [Qemu-devel] [PULL 34/60] target/ppc: introduce single fpr_offset() function, (continued)
- [Qemu-devel] [PULL 34/60] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/10
- [Qemu-devel] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 33/60] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 43/60] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 49/60] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 50/60] ppc/pnv: add a OCC model class, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp using deposit_i64(),
David Gibson <=
- [Qemu-devel] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-devel] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 54/60] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 16/60] PPC: E500: Update u-boot to v2019.01, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 44/60] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 51/60] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 55/60] ppc/pnv: add more dummy XSCOM addresses, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 48/60] ppc/pnv: add a LPC Controller model for POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 52/60] ppc/pnv: extend XSCOM core support for POWER9, David Gibson, 2019/03/10
- [Qemu-devel] [PULL 46/60] ppc/pnv: add a LPC Controller class model, David Gibson, 2019/03/10