[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith |
Date: |
Fri, 1 Mar 2019 13:49:38 -0800 |
From: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +++++++++---------
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++++++-------
target/riscv/translate.c | 4 ++--
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 88ef0003ec17..d420a4d8b2e9 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -307,12 +307,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return trans_arith(ctx, a, &tcg_gen_add_tl);
+ return gen_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return trans_arith(ctx, a, &tcg_gen_sub_tl);
+ return gen_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -322,17 +322,17 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return trans_arith(ctx, a, &gen_slt);
+ return gen_arith(ctx, a, &gen_slt);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return trans_arith(ctx, a, &gen_sltu);
+ return gen_arith(ctx, a, &gen_sltu);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return trans_arith(ctx, a, &tcg_gen_xor_tl);
+ return gen_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -347,12 +347,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return trans_arith(ctx, a, &tcg_gen_or_tl);
+ return gen_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return trans_arith(ctx, a, &tcg_gen_and_tl);
+ return gen_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -399,12 +399,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- return trans_arith(ctx, a, &gen_addw);
+ return gen_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- return trans_arith(ctx, a, &gen_subw);
+ return gen_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
b/target/riscv/insn_trans/trans_rvm.inc.c
index d2bf2f171904..204af225f8f3 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -22,7 +22,7 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &tcg_gen_mul_tl);
+ return gen_arith(ctx, a, &tcg_gen_mul_tl);
}
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
@@ -44,7 +44,7 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_mulhsu);
+ return gen_arith(ctx, a, &gen_mulhsu);
}
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
@@ -66,32 +66,32 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_div);
+ return gen_arith(ctx, a, &gen_div);
}
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_divu);
+ return gen_arith(ctx, a, &gen_divu);
}
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_rem);
+ return gen_arith(ctx, a, &gen_rem);
}
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_remu);
+ return gen_arith(ctx, a, &gen_remu);
}
#ifdef TARGET_RISCV64
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
REQUIRE_EXT(ctx, RVM);
- return trans_arith(ctx, a, &gen_mulw);
+ return gen_arith(ctx, a, &gen_mulw);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3cd7e16c63cf..dedf4189d5b7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -629,8 +629,8 @@ static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
#endif
-static bool trans_arith(DisasContext *ctx, arg_r *a,
- void(*func)(TCGv, TCGv, TCGv))
+static bool gen_arith(DisasContext *ctx, arg_r *a,
+ void(*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
--
2.18.1
- [Qemu-devel] [PULL 22/34] target/riscv: Remove manual decoding from gen_store(), (continued)
- [Qemu-devel] [PULL 22/34] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 11/34] target/riscv: Convert RV32F insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 19/34] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 29/34] target/riscv: Remove decode_RV32_64G(), Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 21/34] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 28/34] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 27/34] target/riscv: Rename trans_arith to gen_arith,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 25/34] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 30/34] target/riscv: Convert @cs_2 insns to share translation functions, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 13/34] target/riscv: Convert RV32D insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/03/01
- [Qemu-devel] [PULL 34/34] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/03/01
- Re: [Qemu-devel] [PULL] target/riscv: Convert to decodetree, Peter Maydell, 2019/03/04