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[Qemu-devel] [PATCH 0/2] target/arm: Use MVFR feature bits to gate some
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 0/2] target/arm: Use MVFR feature bits to gate some insns |
Date: |
Fri, 22 Feb 2019 17:09:34 +0000 |
This patchset switches some of the A32/T32 VFP decode to
look at the relevant MVFR feature bits rather than using
ARM_FEATURE_* feature flags:
* use MVFR1.FPHP and .SIMDHP to gate the FP16 conversion insns
* use MVFR2.FPMISC to gate the various insns in disas_vfp_v8_insn()
This is a bit of preparatory work for v7M/v8M floating point
support: the v7M FPU has the "misc" insns that only arrived
in A-profile in v8, and also the FP16 to/from double precision
conversion insns which are v8-only. So feature checks that look
at ARM_FEATURE_V8 won't work there, and we need to look at the
MVFR* fields instead.
This should have no behavioural changes for current CPUs.
thanks
-- PMM
Peter Maydell (2):
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
target/arm: Gate "miscellaneous FP" insns by ID register field
target/arm/cpu.h | 57 +++++++++++++++++++++++++++++++++++++++++-
target/arm/cpu.c | 2 --
target/arm/kvm32.c | 3 ---
target/arm/translate.c | 47 ++++++++++++++++++++++------------
4 files changed, 87 insertions(+), 22 deletions(-)
--
2.20.1
- [Qemu-devel] [PATCH 0/2] target/arm: Use MVFR feature bits to gate some insns,
Peter Maydell <=