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[Qemu-devel] [PATCH 12/23] tests/tcg/xtensa: conditionalize timer/CCOUNT
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 12/23] tests/tcg/xtensa: conditionalize timer/CCOUNT tests |
Date: |
Mon, 18 Feb 2019 22:11:00 -0800 |
Make timer/CCOUNT tests conditional on the presence of timer option and
number of configured timers. Don't use hard coded interrupt levels for
timers, use configured values.
Signed-off-by: Max Filippov <address@hidden>
---
tests/tcg/xtensa/test_timer.S | 48 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/tests/tcg/xtensa/test_timer.S b/tests/tcg/xtensa/test_timer.S
index 6cda71adbb06..1ec8e20883ff 100644
--- a/tests/tcg/xtensa/test_timer.S
+++ b/tests/tcg/xtensa/test_timer.S
@@ -2,6 +2,8 @@
#define CCOUNT_SHIFT 4
#define WAIT_LOOPS 20
+#define level1 kernel
+#define INTERRUPT_LEVEL(n) glue3(XCHAL_INT, n, _LEVEL)
.macro make_ccount_delta target, delta
rsr \delta, ccount
@@ -13,6 +15,8 @@
test_suite timer
+#if XCHAL_HAVE_CCOUNT
+
test ccount
rsr a3, ccount
rsr a4, ccount
@@ -32,14 +36,20 @@ test ccount_write
assert ltu, a3, a4
test_end
+#if XCHAL_NUM_TIMERS
+
test ccount_update_deadline
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
+#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
+#endif
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
movi a2, 0x12345678
wsr a2, ccompare0
rsr a3, interrupt
@@ -59,8 +69,12 @@ test ccompare
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
+#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
+#endif
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
make_ccount_delta a2, a15
wsr a2, ccompare0
@@ -76,6 +90,7 @@ test ccompare
assert nei, a5, 0
test_end
+#if INTERRUPT_LEVEL(XCHAL_TIMER0_INTERRUPT) == 1
test ccompare0_interrupt
set_vector kernel, 2f
movi a2, 0
@@ -83,8 +98,12 @@ test ccompare0_interrupt
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
+#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
+#endif
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
@@ -104,16 +123,21 @@ test ccompare0_interrupt
rsr a2, exccause
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
test_end
+#endif
+
+#if XCHAL_NUM_TIMERS > 1
test ccompare1_interrupt
- set_vector level3, 2f
+ set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT)), 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
wsr a2, ccompare0
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
movi a3, WAIT_LOOPS
make_ccount_delta a2, a15
@@ -123,7 +147,7 @@ test ccompare1_interrupt
assert eqi, a2, 0
movi a2, 1 << XCHAL_TIMER1_INTERRUPT
wsr a2, intenable
- rsil a2, 2
+ rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER1_INTERRUPT) - 1
loop a3, 1f
nop
1:
@@ -131,8 +155,11 @@ test ccompare1_interrupt
2:
test_end
+#endif
+#if XCHAL_NUM_TIMERS > 2
+
test ccompare2_interrupt
- set_vector level5, 2f
+ set_vector glue(level, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT)), 2f
movi a2, 0
wsr a2, intenable
rsr a2, interrupt
@@ -149,7 +176,7 @@ test ccompare2_interrupt
assert eqi, a2, 0
movi a2, 1 << XCHAL_TIMER2_INTERRUPT
wsr a2, intenable
- rsil a2, 4
+ rsil a2, INTERRUPT_LEVEL(XCHAL_TIMER2_INTERRUPT) - 1
loop a3, 1f
nop
1:
@@ -157,6 +184,8 @@ test ccompare2_interrupt
2:
test_end
+#endif
+
test ccompare_interrupt_masked
set_vector kernel, 2f
movi a2, 0
@@ -164,11 +193,15 @@ test ccompare_interrupt_masked
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
+#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
+#endif
add a2, a2, a15
wsr a2, ccompare0
rsync
@@ -194,11 +227,15 @@ test ccompare_interrupt_masked_waiti
rsr a2, interrupt
wsr a2, intclear
movi a2, 0
+#if XCHAL_NUM_TIMERS > 2
wsr a2, ccompare2
+#endif
movi a3, 2 * WAIT_LOOPS
make_ccount_delta a2, a15
+#if XCHAL_NUM_TIMERS > 1
wsr a2, ccompare1
+#endif
add a2, a2, a15
wsr a2, ccompare0
rsync
@@ -214,4 +251,7 @@ test ccompare_interrupt_masked_waiti
assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */
test_end
+#endif
+#endif
+
test_suite_end
--
2.11.0
- [Qemu-devel] [PATCH 06/23] tests/tcg/xtensa: fix endianness issues in test_b, (continued)
- [Qemu-devel] [PATCH 06/23] tests/tcg/xtensa: fix endianness issues in test_b, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 05/23] tests/tcg/xtensa: don't use optional opcodes in generic code, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 07/23] tests/tcg/xtensa: enable boolean tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 08/23] tests/tcg/xtensa: conditionalize debug option tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 09/23] tests/tcg/xtensa: conditionalize cache option tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 10/23] tests/tcg/xtensa: add straightforward conditionals, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 16/23] tests/tcg/xtensa: conditionalize windowed register tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 13/23] tests/tcg/xtensa: conditionalize and expand SR tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 18/23] tests/tcg/xtensa: add test for FLIX, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 11/23] tests/tcg/xtensa: conditionalize interrupt tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 12/23] tests/tcg/xtensa: conditionalize timer/CCOUNT tests,
Max Filippov <=
- [Qemu-devel] [PATCH 21/23] tests/tcg/xtensa: add FP0 group conversion tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 14/23] tests/tcg/xtensa: fix SR tests for big endian configs, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 15/23] tests/tcg/xtensa: conditionalize and fix s32c1i tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 19/23] tests/tcg/xtensa: add LSCI/LSCX group tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 20/23] tests/tcg/xtensa: add FP0 group arithmetic tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 22/23] tests/tcg/xtensa: add FP1 group tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 17/23] tests/tcg/xtensa: conditionalize MMU-related tests, Max Filippov, 2019/02/19
- [Qemu-devel] [PATCH 23/23] tests/tcg/xtensa: add FPU2000 coprocessor tests, Max Filippov, 2019/02/19