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[Qemu-devel] [PATCH 01/14] hw/arm/armsse: Fix miswiring of expansion IRQ
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 01/14] hw/arm/armsse: Fix miswiring of expansion IRQs |
Date: |
Thu, 14 Feb 2019 12:50:54 +0000 |
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
to external IRQ 1 on CPU 1.
Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/arm/armsse.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 5d53071a5a0..9a8c49547db 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -565,7 +565,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
for (j = 0; j < s->exp_numirq; j++) {
- s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, i + 32);
+ s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + 32);
}
if (i == 0) {
gpioname = g_strdup("EXP_IRQ");
--
2.20.1
- [Qemu-devel] [PATCH 13/14] hw/arm/musca: Wire up PL031 RTC, (continued)
- [Qemu-devel] [PATCH 13/14] hw/arm/musca: Wire up PL031 RTC, Peter Maydell, 2019/02/14
- [Qemu-devel] [PATCH 12/14] hw/arm/musca: Add MPCs, Peter Maydell, 2019/02/14
- [Qemu-devel] [PATCH 11/14] hw/arm/musca: Add PPCs, Peter Maydell, 2019/02/14
- [Qemu-devel] [PATCH 06/14] hw/char/pl011: Support all interrupt lines, Peter Maydell, 2019/02/14
- [Qemu-devel] [PATCH 01/14] hw/arm/armsse: Fix miswiring of expansion IRQs,
Peter Maydell <=
- [Qemu-devel] [PATCH 14/14] hw/arm/musca: Wire up PL011 UARTs, Peter Maydell, 2019/02/14