Re: [Qemu-devel] [PATCH v1] s390x: Add floating-point extension facility to "qemu" cpu model

[David Hildenbrand]

On 12.02.19 12:02, David Hildenbrand wrote:
> The floating-point extension facility implemented certain changes to
> BFP, HFP and DFP instructions.
> 
> As we don't implement HFP/DFP, we can ignore those completely. Related
> to BFP, the changes include
> - SET BFP ROUNDING MODE (SRNMB) instruction
> - BFP-rounding-mode field in the FPC register is changed to 3 bits
> - CONVERT FROM LOGICAL instructions
> - CONVERT TO LOGICAL instructions
> - Changes (rounding mode + XxC) added to
> -- CONVERT TO FIXED
> -- CONVERT FROM FIXED
> -- LOAD FP INTEGER
> -- LOAD ROUNDED
> -- DIVIDE TO INTEGER
> 
> For TCG, we don't implement DIVIDE TO INTEGER, and it is harder to
> implement, so skip that. Also, as we don't implement PFPO, we can skip
> changes to that as well. The other parts are now implemented, we can
> indicate the facility.
> 
> z14 PoP mentiones that "The floating-point extension facility is installed
> in the z/Architecture architectural mode. When bit 37 is one, bit 42 is
> also one.", meaning that the DFP (decimal-floating-point) facility also
> has to be inidicated. We can ignore that for now.
> 
> Signed-off-by: David Hildenbrand <address@hidden>

This is the same patch as 15/15, refer to 0/15 as cover letter instead.

-- 

Thanks,

David / dhildenb