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[Qemu-devel] [PATCH v2 07/12] target/arm: Reset btype for direct branche
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 07/12] target/arm: Reset btype for direct branches |
Date: |
Mon, 28 Jan 2019 14:31:13 -0800 |
This is all of the non-exception cases of DISAS_NORETURN.
Signed-off-by: Richard Henderson <address@hidden>
---
v2: Do not reset byte for syscalls
---
target/arm/translate-a64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bb64a47c0f..dbac09743c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1362,6 +1362,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t
insn)
}
/* B Branch / BL Branch with link */
+ reset_btype(s);
gen_goto_tb(s, 0, addr);
}
@@ -1386,6 +1387,7 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t
insn)
tcg_cmp = read_cpu_reg(s, rt, sf);
label_match = gen_new_label();
+ reset_btype(s);
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
tcg_cmp, 0, label_match);
@@ -1415,6 +1417,8 @@ static void disas_test_b_imm(DisasContext *s, uint32_t
insn)
tcg_cmp = tcg_temp_new_i64();
tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
label_match = gen_new_label();
+
+ reset_btype(s);
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
tcg_cmp, 0, label_match);
tcg_temp_free_i64(tcg_cmp);
@@ -1441,6 +1445,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t
insn)
addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
cond = extract32(insn, 0, 4);
+ reset_btype(s);
if (cond < 0x0e) {
/* genuinely conditional branches */
TCGLabel *label_match = gen_new_label();
@@ -1605,6 +1610,7 @@ static void handle_sync(DisasContext *s, uint32_t insn,
* a self-modified code correctly and also to take
* any pending interrupts immediately.
*/
+ reset_btype(s);
gen_goto_tb(s, 0, s->pc);
return;
default:
--
2.17.2
- [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 09/12] target/arm: Add x-guarded-pages cpu property for user-only, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 05/12] target/arm: Cache the GP bit for a page in MemTxAttrs, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 01/12] target/arm: Introduce isar_feature_aa64_bti, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 08/12] target/arm: Set btype for indirect branches, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 04/12] exec: Add target-specific tlb bits to MemTxAttrs, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 12/12] tests/tcg/aarch64: Add bti smoke test, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 10/12] target/arm: Enable BTI for -cpu max, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 06/12] target/arm: Default handling of BTYPE during translation, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 07/12] target/arm: Reset btype for direct branches,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 02/12] target/arm: Add PSTATE.BTYPE, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 11/12] linux-user/aarch64: Reset btype for syscalls and signals, Richard Henderson, 2019/01/28
- [Qemu-devel] [PATCH v2 03/12] target/arm: Add BT and BTYPE to tb->flags, Richard Henderson, 2019/01/28
- Re: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, no-reply, 2019/01/31
- Re: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, no-reply, 2019/01/31
- Re: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, no-reply, 2019/01/31
- Re: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, no-reply, 2019/01/31
- Re: [Qemu-devel] [PATCH v2 00/12] target/arm: Implement ARMv8.5-BTI, no-reply, 2019/01/31