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[Qemu-devel] [PULL 05/14] target/mips: Extend gen_scwp() functionality t
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 05/14] target/mips: Extend gen_scwp() functionality to support EVA |
Date: |
Fri, 25 Jan 2019 14:31:29 +0100 |
From: Aleksandar Markovic <address@hidden>
Extend gen_scwp() functionality to support EVA by adding an
additional argument, modify internals of the function to handle
new functionality, and accordingly change its invocations.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b362b03..aaf7dff 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -3714,7 +3714,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc,
int rt,
}
static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
- uint32_t reg1, uint32_t reg2)
+ uint32_t reg1, uint32_t reg2, bool eva)
{
TCGv taddr = tcg_temp_local_new();
TCGv lladdr = tcg_temp_local_new();
@@ -3742,7 +3742,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base,
int16_t offset,
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
- ctx->mem_idx, MO_64);
+ eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64);
if (reg1 != 0) {
tcg_gen_movi_tl(cpu_gpr[reg1], 1);
}
@@ -21550,7 +21550,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case NM_SCWP:
check_xnp(ctx);
- gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+ false);
break;
}
break;
@@ -21654,7 +21655,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
+ gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5),
+ true);
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PULL 04/14] target/mips: Correct the second argument type of cpu_supports_isa(), (continued)
- [Qemu-devel] [PULL 04/14] target/mips: Correct the second argument type of cpu_supports_isa(), Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 02/14] target/mips: nanoMIPS: Remove an unused macro, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 08/14] target/mips: Add I6500 core configuration, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 01/14] target/mips: nanoMIPS: Remove duplicate macro definitions, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 09/14] MAINTAINERS: Update MIPS sections, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 11/14] tests: tcg: mips: Add two new Makefiles, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 03/14] target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 07/14] target/mips: nanoMIPS: Fix branch handling, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 13/14] qemu-doc: Add nanoMIPS ISA information, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 14/14] docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 05/14] target/mips: Extend gen_scwp() functionality to support EVA,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 06/14] disas: nanoMIPS: Amend DSP instructions related comments, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 10/14] tests: tcg: mips: Move source files to new locations, Aleksandar Markovic, 2019/01/25
- [Qemu-devel] [PULL 12/14] tests: tcg: mips: Remove old directories, Aleksandar Markovic, 2019/01/25
- Re: [Qemu-devel] [PULL 00/14] MIPS queue for January 25, 2019, Aleksandar Markovic, 2019/01/25
- Re: [Qemu-devel] [PULL 00/14] MIPS queue for January 25, 2019, Peter Maydell, 2019/01/25