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Re: [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR
From: |
Stefan Markovic |
Subject: |
Re: [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers |
Date: |
Thu, 17 Jan 2019 14:59:52 +0000 |
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim <address@hidden>
>
> Add fields for SAARI and SAAR CP0 registers.
>
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> target/mips/cpu.h | 10 ++++++++--
> target/mips/machine.c | 6 ++++--
> 2 files changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Stefan Markovic <address@hidden>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index b095422..1c2c682 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
> * 3 BadInstrX
> * 4 GuestCtl1 GuestCtl0Ext
> * 5 GuestCtl2
> - * 6 GuestCtl3
> - * 7
> + * 6 SAARI GuestCtl3
> + * 7 SAAR
> *
> *
> * Register 12 Register 13 Register 14 Register 15
> @@ -546,6 +546,12 @@ struct CPUMIPSState {
> * CP0 Register 9
> */
> int32_t CP0_Count;
> + uint32_t CP0_SAARI;
> +#define CP0SAARI_TARGET 0 /* 5..0 */
> + uint64_t CP0_SAAR[2];
> +#define CP0SAAR_BASE 12 /* 43..12 */
> +#define CP0SAAR_SIZE 1 /* 5..1 */
> +#define CP0SAAR_EN 0
> /*
> * CP0 Register 10
> */
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 704e9c0..111d7c3 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
>
> const VMStateDescription vmstate_mips_cpu = {
> .name = "cpu",
> - .version_id = 15,
> - .minimum_version_id = 15,
> + .version_id = 16,
> + .minimum_version_id = 16,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> /* Active TC */
> @@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
> VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
> VMSTATE_INT32(env.CP0_Count, MIPSCPU),
> + VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
> + VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
> VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
> VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
> VMSTATE_INT32(env.CP0_Status, MIPSCPU),
- Re: [Qemu-devel] [PATCH 5/8] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, (continued)
- [Qemu-devel] [PATCH 1/8] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 3/8] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- Re: [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers,
Stefan Markovic <=
- Re: [Qemu-devel] [PATCH 0/8] target/mips: Update Inter-Thread Communication Unit support, no-reply, 2019/01/23