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[Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extensio
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension |
Date: |
Thu, 13 Dec 2018 14:54:41 +0000 |
From: Richard Henderson <address@hidden>
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
interpret the bits as if ARMv8.1-HPD is present without checking.
We will need a slightly different check for hpd for aarch32.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu64.c | 4 ++++
target/arm/helper.c | 27 ++++++++++++++++++++-------
2 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0babe483ac2..1a4289c9dda 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
cpu->isar.id_aa64pfr0 = t;
+ t = cpu->isar.id_aa64mmfr1;
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
+ cpu->isar.id_aa64mmfr1 = t;
+
/* Replicate the same data to the 32-bit id registers. */
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1dad277804f..57af6b77a1b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9636,6 +9636,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
bool ttbr1_valid = true;
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
+ bool hpd = false;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -9750,6 +9751,13 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (tg == 2) { /* 16KB pages */
stride = 11;
}
+ if (aarch64) {
+ if (el > 1) {
+ hpd = extract64(tcr->raw_tcr, 24, 1);
+ } else {
+ hpd = extract64(tcr->raw_tcr, 41, 1);
+ }
+ }
} else {
/* We should only be here if TTBR1 is valid */
assert(ttbr1_valid);
@@ -9765,6 +9773,9 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (tg == 1) { /* 16KB pages */
stride = 11;
}
+ if (aarch64) {
+ hpd = extract64(tcr->raw_tcr, 42, 1);
+ }
}
/* Here we should have set up all the parameters for the translation:
@@ -9858,7 +9869,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
descaddr = descriptor & descaddrmask;
if ((descriptor & 2) && (level < 3)) {
- /* Table entry. The top five bits are attributes which may
+ /* Table entry. The top five bits are attributes which may
* propagate down through lower levels of the table (and
* which are all arranged so that 0 means "no effect", so
* we can gather them up by ORing in the bits at each level).
@@ -9883,15 +9894,17 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
break;
}
/* Merge in attributes from table descriptors */
- attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
- attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
+ attrs |= nstable << 3; /* NS */
+ if (hpd) {
+ /* HPD disables all the table attributes except NSTable. */
+ break;
+ }
+ attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
* means "force PL1 access only", which means forcing AP[1] to 0.
*/
- if (extract32(tableattrs, 2, 1)) {
- attrs &= ~(1 << 4);
- }
- attrs |= nstable << 3; /* NS */
+ attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
+ attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
break;
}
/* Here descaddr is the final physical address, and attributes
--
2.19.2
- [Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB, (continued)
- [Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension,
Peter Maydell <=
- [Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 26/37] hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 25/37] hw/arm: versal: Reduce number of virtio-mmio instances, Peter Maydell, 2018/12/13
- [Qemu-devel] [PULL 23/37] core/sysbus: remove the SysBusDeviceClass::init path, Peter Maydell, 2018/12/13