[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v10 08/14] target/arm: Make PMCEID[01]_EL0 64 bit re
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v10 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] |
Date: |
Tue, 11 Dec 2018 15:20:35 +0000 |
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 4 ++--
target/arm/helper.c | 19 +++++++++++++++++--
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2a64c1d858..ed3ec81d16 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -837,8 +837,8 @@ struct ARMCPU {
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
- uint32_t pmceid0;
- uint32_t pmceid1;
+ uint64_t pmceid0;
+ uint64_t pmceid1;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 71be6fb578..cbbd56858c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5256,6 +5256,21 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else {
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
}
+ if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
+ FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
+ ARMCPRegInfo v81_pmu_regs[] = {
+ { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+ .resetvalue = extract64(cpu->pmceid0, 32, 32) },
+ { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
+ .resetvalue = extract64(cpu->pmceid1, 32, 32) },
+ REGINFO_SENTINEL
+ };
+ define_arm_cp_regs(cpu, v81_pmu_regs);
+ }
if (arm_feature(env, ARM_FEATURE_V8)) {
/* AArch64 ID registers, which all have impdef reset values.
* Note that within the ID register ranges the unused slots
@@ -5432,7 +5447,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
- .resetvalue = cpu->pmceid0 },
+ .resetvalue = extract64(cpu->pmceid0, 0, 32) },
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
@@ -5440,7 +5455,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
- .resetvalue = cpu->pmceid1 },
+ .resetvalue = extract64(cpu->pmceid1, 0, 32) },
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
--
2.19.2
- [Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 01/14] migration: Add post_save function to VMStateDescription, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 03/14] target/arm: Swap PMU values before/after migrations, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 02/14] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 06/14] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 05/14] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 07/14] target/arm: Define FIELDs for ID_DFR0, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23],
Aaron Lindsay <=
- [Qemu-devel] [PATCH v10 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 11/14] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 13/14] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 12/14] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/12/11
- [Qemu-devel] [PATCH v10 14/14] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/12/11