[Qemu-devel] Question about piix3's PIRQC register set

[Li Qiang]

Hello Paolo Alex, and all,

I have a question when reading the ‘vfio_intx_enable’ function.

There calls ‘pci_device_route_intx_to_irq’ to get the ‘irq number’ from 
a device intx info.

It is read from ‘piix3->dev.config[PIIX_PIRQC + pin];’ in 
‘piix3_route_intx_pin_to_irq’.

Here my question when the piix3’s PIRQx route control registers is set and by 
who?
I mean when this ‘‘piix3->dev.config[PIIX_PIRQC + pin];’’ is set?

Once I think this is set by seabios. 
But seems it is not as this function is called in vfio_realize, the guest 
dones’t begin.

Thanks,
Li Qiang