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[Qemu-devel] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitt
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitters |
Date: |
Tue, 27 Nov 2018 21:07:58 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 40 ++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index c659c4de39..ca7ae8939a 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -343,6 +343,46 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd,
uint32_t imm)
return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm);
}
+/*
+ * RISC-V instruction emitters
+ */
+
+static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+ tcg_out32(s, encode_r(opc, rd, rs1, rs2));
+}
+
+static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, TCGReg rs1, TCGArg imm)
+{
+ tcg_out32(s, encode_i(opc, rd, rs1, imm));
+}
+
+static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_s(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
+ TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+ tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_u(opc, rd, imm));
+}
+
+static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+ tcg_out32(s, encode_uj(opc, rd, imm));
+}
+
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
uintptr_t addr)
{
--
2.19.1
- [Qemu-devel] [RFC v2 02/24] linux-user: Add host dependency for RISC-V 32-bit, (continued)
- [Qemu-devel] [RFC v2 02/24] linux-user: Add host dependency for RISC-V 32-bit, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 03/24] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 04/24] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 05/24] riscv: Add the tcg-target header file, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 06/24] riscv: Add the tcg target registers, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 07/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 08/24] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitters,
Alistair Francis <=
- [Qemu-devel] [RFC v2 10/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 12/24] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 13/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-devel] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/11/27