Re: [Qemu-devel] [PATCH 10/10] pvpanic : update pvpanic document

[peng.hao2]

I'm sorry to sent patches with unmodified title. 
Please ignore patch 1-10. I will re-send.
>Add mmio support info in docs/specs/pvpanic.txt.
>
>Signed-off-by: Peng Hao <address@hidden>
>---
>docs/specs/pvpanic.txt | 18 +++++++++++++++---
>1 file changed, 15 insertions(+), 3 deletions(-)
>
>diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
>index c7bbacc..2d06ee5 100644
>--- a/docs/specs/pvpanic.txt
>+++ b/docs/specs/pvpanic.txt
>@@ -1,14 +1,18 @@
>PVPANIC DEVICE
>==============
>-pvpanic device is a simulated ISA device, through which a guest panic
>-event is sent to qemu, and a QMP event is generated. This allows
>+pvpanic device is a simulated ISA/SysBus device, through which a guest
>+panic event is sent to qemu, and a QMP event is generated. This allows
>management apps (e.g. libvirt) to be notified and respond to the event.
>-The management app has the option of waiting for GUEST_PANICKED events,
>+The ma:wqnagement app has the option of waiting for GUEST_PANICKED events,
>and/or polling for guest-panicked RunState, to learn when the pvpanic
>device has fired a panic event.
>+When pvpanic device is implemented as a ISA device, it supports IOPORT
>+mode. Since QEMU v3.2 pvpanic also supports MMIO mode, it will be
>+implemented as a SYSBUS device.
>+
>ISA Interface
>-------------
>@@ -19,6 +23,14 @@ Software should set only bits both itself and the device 
>recognize.
>Currently, only bit 0 is recognized, setting it indicates a guest panic
>has happened.
>+SYSBUS Interface
>+----------------
>+
>+The SYSBUS interface is similar to the ISA interface except that it uses
>+MMIO. For example, the arm virt machine could put the pvpanic device at
>+[0x9070000, 0x9070001] and currently only the first byte is used.
>+
>+
>ACPI Interface
>--------------
>--
>1.8.3.1