Re: [Qemu-devel] [PATCH for-3.2 v7 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe

[Alistair Francis]

On Wed, Nov 21, 2018 at 11:25 AM Logan Gunthorpe <address@hidden> wrote:
>
>
>
> On 2018-11-21 12:21 p.m., Alistair Francis wrote:
> > On Wed, Nov 21, 2018 at 11:19 AM Logan Gunthorpe <address@hidden> wrote:
> >> Well, I also have a kernel (one I've built myself) without microsemi
> >> support, but with Xilinx support and it also doesn't work (see my dmesg
> >> logs I sent).
> >
> > So this one should work.
>
> It does not, see the dmesgs I sent a few emails ago.
>
> >>
> >>> For people who have modified the standard bbl to edit the device tree
> >>> before passing it to Linux to add the MicroSemi PCIe node, it won't
> >>> work. That's a very small number of people who have modified the
> >>> standard boot loader. I don't think we need to document how those
> >>> people get back to the default set-up.
> >>
> >> I have not done that. And it's not working for me.
> >
> > If you haven't done this then how can Linux know to probe the
> > MicroSemi PCIe root complex?
>
> Oh, well actually, in this case I was using the bbl/kernel you sent us,
> so I'm not actually sure what's in it. The stuff I built myself doesn't
> have any of the microsemi stuff, so it sounds like all that was a red
> herring.

Ah ok. There was some confusion there then.

So now it sounds like it's not working and there is no MicroSemi
device. I will check and see what I find.

Alistair

>
> Logan