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Re: [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init c
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From: |
Alistair Francis |
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Subject: |
Re: [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code |
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Date: |
Mon, 19 Nov 2018 15:04:53 -0800 |
On Fri, Nov 16, 2018 at 9:26 AM Richard Henderson
<address@hidden> wrote:
>
> On 11/15/18 11:36 PM, Alistair Francis wrote:
> > + tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
> > + tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
> > + tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
>
> Why are these three reserved?
Do these not need to be? I thought we had to reserve them.
Alistair
>
>
> r~
[Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/11/15
[Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/11/15
[Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/11/15
Re: [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/11/16