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Re: [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler |
Date: |
Fri, 16 Nov 2018 18:29:13 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 |
On 11/15/18 11:37 PM, Alistair Francis wrote:
> + /* Detect store by reading the instruction at the program
> + counter. Note: we currently only generate 32-bit
> + instructions so we thus only detect 32-bit stores */
Actually, you need to handle what the compiler generates too. So, if
__riscv_compressed is defined, you need to handle it.
r~
- [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions, (continued)
- [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support, Alistair Francis, 2018/11/15
- [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host, Alistair Francis, 2018/11/15
- Re: [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support, no-reply, 2018/11/16