[Qemu-devel] [RFC PATCH 1/3] i386: add properties for customizing L2 and L3 caches size

[Dario Faggioli]

Make it possible to specify a custom size for the L2 and
L3 caches, from the command line.

This can be useful in cases where applications or libraries
check, within the guest, the cache size and behave differently
depending on what they actually see.

Signed-off-by: Dario Faggioli <address@hidden>
---
I am not entirely sure I got the include/hw/i386 bits right (i.e.,
whether I should include the new properties in PC_COMPAT_3_0 and, if
yes, if the stanzas are correct). I'll dig further (and accept any
help/advice :-D )
---
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
---
 0 files changed

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 136fe497b6..1094bba68c 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -308,6 +308,14 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
         .driver   = "Skylake-Server-IBRS" "-" TYPE_X86_CPU,\
         .property = "pku",\
         .value    = "off",\
+    },{\
+        .driver   = TYPE_X86_CPU,\
+        .property = "l3-cache-size",\
+        .value    = "off",\
+    },{\
+        .driver   = TYPE_X86_CPU,\
+        .property = "l2-cache-size",\
+        .value    = "off",\
     },
 
 #define PC_COMPAT_2_12 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f81d35e1f9..b8ccb2be04 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5778,6 +5778,14 @@ static Property x86_cpu_properties[] = {
     DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
     DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
                      false),
+
+    /*
+     * Custom size for L2 and/or L3 cache. Default (0) means we use the
+     * default value for the CPU.
+     */
+    DEFINE_PROP_SIZE("l2-cache-size", X86CPU, l2_cache_size, 0),
+    DEFINE_PROP_SIZE("l3-cache-size", X86CPU, l3_cache_size, 0),
+
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 9c52d0cbeb..ba0b913448 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1476,6 +1476,9 @@ struct X86CPU {
     int32_t core_id;
     int32_t thread_id;
 
+    uint64_t l2_cache_size;
+    uint64_t l3_cache_size;
+
     int32_t hv_max_vps;
 };