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Re: [Qemu-devel] [PATCH v1 0/3] intel-iommu: add support for 5-level vir
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From: |
Peter Xu |
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Subject: |
Re: [Qemu-devel] [PATCH v1 0/3] intel-iommu: add support for 5-level virtual IOMMU. |
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Date: |
Mon, 12 Nov 2018 16:53:31 +0800 |
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User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Fri, Nov 09, 2018 at 07:49:44PM +0800, Yu Zhang wrote:
> Intel's upcoming processors will extend maximum linear address width to
> 57 bits, and introduce 5-level paging for CPU. Meanwhile, the platform
> will also extend the maximum guest address width for IOMMU to 57 bits,
> thus introducing the 5-level paging for 2nd level translation(See chapter 3
> in Intel Virtualization Technology for Directed I/O).
>
> This patch set extends the current logic to support a wider address width.
> A 5-level paging capable IOMMU(for 2nd level translation) can be rendered
> with configuration "device intel-iommu,x-aw-bits=57".
Along with this series, I'm not sure whether it'll be good we start to
consider removing the "x-" prefix for "x-aw-bits".
Michael?
Regards,
--
Peter Xu