Re: [Qemu-devel] [PULL v3 00/10] target-arm queue

[Peter Maydell]

On 2 November 2018 at 17:16, Peter Maydell <address@hidden> wrote:
> This is a respin of my pull request from earlier this week:
>  * versal board compile failure fixed
>  * a few new patches:
>   - MAINTAINERS file fix
>   - use ARRAY_SIZE macro in xilinx_zynq
>   - avoid an array overrun in strongarm GPIO irq handling
>   - fix an assert running KVM on an aarch64-only host
>
> The following changes since commit 69e2d03843412b9c076515b3aa9a71db161b6a1a:
>
>   Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' 
> into staging (2018-11-02 13:16:13 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20181102
>
> for you to fetch changes up to 6f16da53ffe4567c0353f85055df04860eb4e6fc:
>
>   hw/arm: versal: Add a virtual Xilinx Versal board (2018-11-02 14:11:31 
> +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * microbit: Add the UART to our nRF51 SoC model
>  * Add a virtual Xilinx Versal board "xlnx-versal-virt"
>  * hw/arm/virt: Set VIRT_COMPAT_3_0 compat
>  * MAINTAINERS: Remove bouncing email in ARM ACPI
>  * strongarm: mask off high[31:28] bits from dir and state registers
>  * target/arm: Conditionalize some asserts on aarch32 support
>  * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM