|
From: | Bastian Koppelmann |
Subject: | Re: [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D insns to decodetree |
Date: | Wed, 31 Oct 2018 11:44:27 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 |
On 10/20/18 9:14 AM, Bastian Koppelmann wrote: [...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn) +{ +#if defined(TARGET_RISCV64) + REQUIRE_FPU; + + TCGv t0 = tcg_temp_new(); + gen_helper_fclass_d(t0, cpu_fpr[a->rs1]); + gen_set_gpr(a->rd, t0); + tcg_temp_free(t0); +#else + gen_exception_illegal(ctx); +#endif + return true; +}
I'm a bit confused here. According to the spec fclass_d is a RV32F instruction but according to the original qemu code it is not?
Cheers, Bastian
[Prev in Thread] | Current Thread | [Next in Thread] |