Re: [Qemu-devel] [PULL 2/3] target/mips: Implement emulation of nanoMIPS EVA instructions

[Peter Maydell]

On 25 October 2018 at 21:19, Aleksandar Markovic
<address@hidden> wrote:
> From: Dimitrije Nikolic <address@hidden>
>
> Implement emulation of nanoMIPS EVA instructions. They are all
> part of P.LS.E0 instruction pool, or one of its subpools.
>
> Reviewed-by: Stefan Markovic <address@hidden>
> Signed-off-by: Dimitrije Nikolic <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> --

Hi; Coverity points out (CID 1396475) that the switch
cases for NM_LLWPE and NM_SCWPE fall through without
either a 'break' statement or a '/* fall through */' comment:

> +                case NM_P_LLE:
> +                    switch (extract32(ctx->opcode, 2, 2)) {
> +                    case NM_LLE:
> +                        check_xnp(ctx);
> +                        check_eva(ctx);
> +                        check_cp0_enabled(ctx);
> +                        gen_ld(ctx, OPC_LLE, rt, rs, s);
> +                        break;
> +                    case NM_LLWPE:
> +                        check_xnp(ctx);
> +                        check_eva(ctx);
> +                        check_cp0_enabled(ctx);
> +                        gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5));
> +                    default:
> +                        generate_exception_end(ctx, EXCP_RI);
> +                        break;
> +                    }
> +                    break;
> +                case NM_P_SCE:
> +                    switch (extract32(ctx->opcode, 2, 2)) {
> +                    case NM_SCE:
> +                        check_xnp(ctx);
> +                        check_eva(ctx);
> +                        check_cp0_enabled(ctx);
> +                        gen_st_cond(ctx, OPC_SCE, rt, rs, s);
> +                        break;
> +                    case NM_SCWPE:
> +                        check_xnp(ctx);
> +                        check_eva(ctx);
> +                        check_cp0_enabled(ctx);
> +                        gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 
> 5));
> +                    default:
> +                        generate_exception_end(ctx, EXCP_RI);
> +                        break;
> +                    }
> +                    break;
> +                }
> +                break;
>              case NM_P_LS_WM:
>              case NM_P_LS_UAWM:
>                  check_nms(ctx);

Could you send a patch which adds whichever of the two is correct, please?

thanks
-- PMM