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[Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-o
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1 |
Date: |
Wed, 24 Oct 2018 15:40:38 +0200 |
From: Fredrik Noring <address@hidden>
Add a test for MULT1.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
tests/tcg/mips/mipsr5900/mult.c | 45 +++++++++++++++++++++++++++++++++--------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/mult.c b/tests/tcg/mips/mipsr5900/mult.c
index 2c0c16d..5710b39 100644
--- a/tests/tcg/mips/mipsr5900/mult.c
+++ b/tests/tcg/mips/mipsr5900/mult.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MULT.
+ * Test R5900-specific three-operand MULT and MULT1.
*/
#include <stdio.h>
@@ -25,12 +25,41 @@ static int64_t mult(int32_t rs, int32_t rt)
return r;
}
+static int64_t mult1(int32_t rs, int32_t rt)
+{
+ int32_t rd, lo, hi;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mult1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert((int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t mult_variants(int32_t rs, int32_t rt)
+{
+ int64_t rd = mult(rs, rt);
+ int64_t rd1 = mult1(rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
static void verify_mult_negations(int32_t rs, int32_t rt, int64_t expected)
{
- assert(mult(rs, rt) == expected);
- assert(mult(-rs, rt) == -expected);
- assert(mult(rs, -rt) == -expected);
- assert(mult(-rs, -rt) == expected);
+ assert(mult_variants(rs, rt) == expected);
+ assert(mult_variants(-rs, rt) == -expected);
+ assert(mult_variants(rs, -rt) == -expected);
+ assert(mult_variants(-rs, -rt) == expected);
}
int main()
@@ -39,9 +68,9 @@ int main()
verify_mult_negations(77773, 99991, 7776600043);
verify_mult_negations(12207031, 305175781, 3725290219116211);
- assert(mult(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
- assert(mult(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
- assert(mult(-0x80000000, -0x80000000) == 0x4000000000000000);
+ assert(mult_variants(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
+ assert(mult_variants(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(mult_variants(-0x80000000, -0x80000000) == 0x4000000000000000);
return 0;
}
--
2.7.4
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, (continued)
- [Qemu-devel] [PULL v2 03/33] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 11/33] target/mips: Add a placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 14/33] target/mips: Add a placeholder for R5900 MMI2 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 16/33] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 05/33] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 06/33] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 12/33] target/mips: Add a placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 08/33] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 20/33] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 29/33] tests/tcg/mips: Add tests for R5900 DIVU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 24/33] tests/tcg/mips: Add tests for R5900 three-operand MULT1,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 17/33] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 23/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 18/33] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 30/33] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 26/33] tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 22/33] tests/tcg/mips: Add tests for R5900 three-operand MULT, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 25/33] tests/tcg/mips: Add tests for R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 21/33] target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 15/33] target/mips: Add a placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PULL v2 19/33] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/24