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[Qemu-devel] [PATCH v7 12/20] target/mips: Add emulation of MXU instruct
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v7 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I |
Date: |
Wed, 24 Oct 2018 14:18:39 +0200 |
From: Craig Janeczek <address@hidden>
Add support for emulating the S32I2M and S32M2I MXU instructions.
This commit also contains utility functions for reading/writing
to MXU registers. This is required for overall MXU instruction
support.
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 84 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 29df4ce..c8c71c4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2575,6 +2575,35 @@ static inline void gen_store_srsgpr (int from, int to)
}
}
+/* MXU General purpose registers moves. */
+static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg)
+{
+ if (reg == 0) {
+ tcg_gen_movi_tl(t, 0);
+ } else if (reg <= 15) {
+ tcg_gen_mov_tl(t, mxu_gpr[reg - 1]);
+ }
+}
+
+static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg)
+{
+ if (reg > 0 && reg <= 15) {
+ tcg_gen_mov_tl(mxu_gpr[reg - 1], t);
+ }
+}
+
+/* MXU control register moves. */
+static inline void gen_load_mxu_cr(TCGv t)
+{
+ tcg_gen_mov_tl(t, mxu_CR);
+}
+
+static inline void gen_store_mxu_cr(TCGv t)
+{
+ tcg_gen_mov_tl(mxu_CR, t);
+}
+
+
/* Tests */
static inline void gen_save_pc(target_ulong pc)
{
@@ -23879,6 +23908,59 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
/*
+ * S32I2M XRa, rb - Register move from GRF to XRF
+ */
+static void gen_mxu_s32i2m(DisasContext *ctx)
+{
+ TCGv t0;
+ uint32_t XRa, Rb;
+
+ t0 = tcg_temp_new();
+
+ XRa = extract32(ctx->opcode, 6, 5);
+ Rb = extract32(ctx->opcode, 16, 5);
+
+ gen_load_gpr(t0, Rb);
+ if (XRa <= 15) {
+ gen_store_mxu_gpr(t0, XRa);
+ } else if (XRa == 16) {
+ gen_store_mxu_cr(t0);
+ }
+
+ tcg_temp_free(t0);
+}
+
+/*
+ * S32M2I XRa, rb - Register move from XRF to GRF
+ */
+static void gen_mxu_s32m2i(DisasContext *ctx)
+{
+ TCGv t0;
+ uint32_t XRa, Rb;
+
+ t0 = tcg_temp_new();
+
+ XRa = extract32(ctx->opcode, 6, 5);
+ Rb = extract32(ctx->opcode, 16, 5);
+
+ if (XRa <= 15) {
+ gen_load_mxu_gpr(t0, XRa);
+ } else if (XRa == 16) {
+ gen_load_mxu_cr(t0);
+ }
+
+ gen_store_gpr(t0, Rb);
+
+ tcg_temp_free(t0);
+}
+
+
+/*
+ * Decoding engine for MXU
+ * =======================
+ */
+
+/*
*
* Decode MXU pool00
*
@@ -24952,14 +25034,10 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_MXU_S32M2I:
- /* TODO: Implement emulation of S32M2I instruction. */
- MIPS_INVAL("OPC_MXU_S32M2I");
- generate_exception_end(ctx, EXCP_RI);
+ gen_mxu_s32m2i(ctx);
break;
case OPC_MXU_S32I2M:
- /* TODO: Implement emulation of S32I2M instruction. */
- MIPS_INVAL("OPC_MXU_S32I2M");
- generate_exception_end(ctx, EXCP_RI);
+ gen_mxu_s32i2m(ctx);
break;
case OPC_MXU_D32SLL:
/* TODO: Implement emulation of D32SLL instruction. */
--
2.7.4
- [Qemu-devel] [PATCH v7 08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', (continued)
- [Qemu-devel] [PATCH v7 08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 09/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 10/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 14/20] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 17/20] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/24
- [Qemu-devel] [PATCH v7 15/20] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/24