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[Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers |
Date: |
Tue, 23 Oct 2018 18:18:12 +0200 |
From: Craig Janeczek <address@hidden>
Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 10 ++++++++++
target/mips/translate.c | 20 ++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e48be4b..03c03fd 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -170,6 +170,16 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
+
+#define NUMBER_OF_MXU_REGISTERS 16
+ target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+ target_ulong mxu_cr;
+#define MXU_CR_LC 31
+#define MXU_CR_RC 30
+#define MXU_CR_BIAS 2
+#define MXU_CR_RD_EN 1
+#define MXU_CR_MXU_EN 0
+
};
typedef struct CPUMIPSState CPUMIPSState;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 92df8da..c1f692c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2379,6 +2379,10 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
static TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
+/* MXU registers */
+static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
+static TCGv mxu_CR;
+
#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
@@ -2501,6 +2505,11 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
+static const char * const mxuregnames[] = {
+ "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
+ "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
+};
+
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@@ -27091,6 +27100,17 @@ void mips_tcg_init(void)
fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMIPSState,
active_fpu.fcr31),
"fcr31");
+
+ for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
+ mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState,
+ active_tc.mxu_gpr[i]),
+ mxuregnames[i]);
+ }
+
+ mxu_CR = tcg_global_mem_new(cpu_env,
+ offsetof(CPUMIPSState, active_tc.mxu_cr),
+ mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
}
#include "translate_init.inc.c"
--
2.7.4
- [Qemu-devel] [PATCH v6 00/18] target/mips: Add limited support for Ingenic's MXU ASE, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 01/18] target/mips: Introduce MXU registers,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v6 02/18] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 04/18] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 03/18] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 05/18] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 06/18] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 07/18] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 08/18] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 09/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 10/18] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/23
- [Qemu-devel] [PATCH v6 11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/23