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[Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode cons
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants |
Date: |
Sun, 21 Oct 2018 17:34:46 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bd51443ac1..3c6a2c99a6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2323,6 +2323,45 @@ enum {
TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI3:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI3 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 |PMADDUW| * | * | PSRAVW
+ * 1 001 | * | * | * | *
+ * 2 010 | PMTHI | PMTLO | PINTEH| *
+ * 3 011 |PMULTUW| PDIVUW| PCPYUD| *
+ * 4 100 | * | * | POR | PNOR
+ * 5 101 | * | * | * | *
+ * 6 110 | * | * | PEXCH | PCPYH
+ * 7 111 | * | * | PEXCW | *
+ */
+
+#define MASK_TX79_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI3_PMADDUW = (0x00 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PSRAVW = (0x03 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMTHI = (0x08 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMTLO = (0x09 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PINTEH = (0x0A << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMULTUW = (0x0C << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PDIVUW = (0x0D << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PCPYUD = (0x0E << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_POR = (0x12 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PNOR = (0x13 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PEXCH = (0x1A << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PCPYH = (0x1B << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PEXCW = (0x1E << 6) | TX79_MMI_CLASS_MMI3,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
- [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 02/38] disas/mips: Define R5900 disassembly constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 03/38] target/mips: R5900 Multimedia Instruction overview note, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 opcode constants, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1, Fredrik Noring, 2018/10/21