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Re: [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU
From: |
Aleksandar Markovic |
Subject: |
Re: [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2' |
Date: |
Fri, 19 Oct 2018 17:12:05 +0000 |
> From: Aleksandar Markovic <> address@hidden>
> Sent: Friday, October 19, 2018 6:33 PM
> Subject: [PATCH v5 05/14] target/mips: > Add bit encoding for MXU
> add/subtract > patterns 'aptn2'
>
> From: Craig Janeczek <> address@hidden>
>
> Add bit encoding for MXU add/subtract patterns 'aptn2'.
>
'eptn2' is very similar to 'aptn2', but we need a similar patch for 'eptn2' too.
This is needed so that we are as close to the documentation as possible.
'aptn1' and 'strd2', in my opinion, do not need any preprocessor definition,
since they can be only 0 and 1, and 0, 1, 2 respectively... What do you think,
Craig?
Thanks,
Aleksandar
> Signed-off-by: Craig Janeczek <> address@hidden>
> Signed-off-by: Aleksandar Markovic <> address@hidden>
> ---
> target/mips/translate.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/mips/translate.c b/> target/mips/translate.c
> index 5f8dcc9..f465635 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23311,6 +23311,13 @@ static void > decode_opc_special(CPUMIPSState *env,
> > DisasContext *ctx)
> }
> }
>
> +/* MXU add/subtract patterns 'aptn2' */
> +#define MXU_APTN2_AA 0
> +#define MXU_APTN2_AS 1
> +#define MXU_APTN2_SA 2
> +#define MXU_APTN2_SS 3
> +
> +
> /*
> *
> * Decode MXU pool00
> --
> 2.7.4
>
- [Qemu-devel] [PATCH v5 00/14] Add limited MXU instruction support, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 01/14] target/mips: Introduce MXU registers, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 02/14] target/mips: Define a bit for MXU in insn_flags, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 03/14] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 04/14] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2', Aleksandar Markovic, 2018/10/19
- Re: [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2',
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 14/14] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 07/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn3', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 06/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 10/14] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 11/14] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 09/14] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 12/14] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 13/14] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/19